## Top method regressions
35 (3.54 % of base) - System.IO.Hashing.XxHash3:HashLength129To240(ptr,uint,ulong):ulong
```diff
; Assembly listing for method System.IO.Hashing.XxHash3:HashLength129To240(ptr,uint,ulong):ulong (FullOpts)
; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix
; FullOpts code
; optimized code
; rbp based frame
; partially interruptible
; No PGO data
; 0 inlinees with PGO data; 54 single block inlinees; 48 inlinees without PGO data
; Final local variable assignments
;
; V00 arg0 [V00,T01] ( 19, 15.50) long -> rdi single-def
; V01 arg1 [V01,T06] ( 5, 5 ) int -> rsi single-def
; V02 arg2 [V02,T02] ( 19, 15.50) long -> [rbp-0x08] single-def
-; V03 loc0 [V03,T00] ( 32, 25 ) long -> rcx
+; V03 loc0 [V03,T00] ( 32, 25 ) long -> rax
;* V04 loc1 [V04 ] ( 0, 0 ) int -> zero-ref
;# V05 OutArgs [V05 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;* V06 tmp1 [V06 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
;* V07 tmp2 [V07 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V08 tmp3 [V08 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V09 tmp4 [V09 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V10 tmp5 [V10 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V11 tmp6 [V11 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp"
;* V12 tmp7 [V12 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
;* V13 tmp8 [V13 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V14 tmp9 [V14 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return"
;* V15 tmp10 [V15 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp"
-; V16 tmp11 [V16,T07] ( 3, 6 ) long -> rax "Inlining Arg"
+; V16 tmp11 [V16,T07] ( 3, 6 ) long -> rdx "Inlining Arg"
;* V17 tmp12 [V17 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
;* V18 tmp13 [V18 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V19 tmp14 [V19 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V20 tmp15 [V20 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V21 tmp16 [V21 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V22 tmp17 [V22 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp"
;* V23 tmp18 [V23 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
;* V24 tmp19 [V24 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V25 tmp20 [V25 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return"
;* V26 tmp21 [V26 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp"
-; V27 tmp22 [V27,T08] ( 3, 6 ) long -> rax "Inlining Arg"
+; V27 tmp22 [V27,T08] ( 3, 6 ) long -> rdx "Inlining Arg"
;* V28 tmp23 [V28 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
;* V29 tmp24 [V29 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V30 tmp25 [V30 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V31 tmp26 [V31 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V32 tmp27 [V32 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V33 tmp28 [V33 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp"
;* V34 tmp29 [V34 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
;* V35 tmp30 [V35 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V36 tmp31 [V36 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return"
;* V37 tmp32 [V37 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp"
-; V38 tmp33 [V38,T09] ( 3, 6 ) long -> rax "Inlining Arg"
+; V38 tmp33 [V38,T09] ( 3, 6 ) long -> rdx "Inlining Arg"
;* V39 tmp34 [V39 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
;* V40 tmp35 [V40 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V41 tmp36 [V41 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V42 tmp37 [V42 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V43 tmp38 [V43 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V44 tmp39 [V44 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp"
;* V45 tmp40 [V45 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
;* V46 tmp41 [V46 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V47 tmp42 [V47 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return"
;* V48 tmp43 [V48 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp"
-; V49 tmp44 [V49,T10] ( 3, 6 ) long -> rax "Inlining Arg"
+; V49 tmp44 [V49,T10] ( 3, 6 ) long -> rdx "Inlining Arg"
;* V50 tmp45 [V50 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
;* V51 tmp46 [V51 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V52 tmp47 [V52 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V53 tmp48 [V53 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V54 tmp49 [V54 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V55 tmp50 [V55 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp"
;* V56 tmp51 [V56 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
;* V57 tmp52 [V57 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V58 tmp53 [V58 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return"
;* V59 tmp54 [V59 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp"
-; V60 tmp55 [V60,T11] ( 3, 6 ) long -> rax "Inlining Arg"
+; V60 tmp55 [V60,T11] ( 3, 6 ) long -> rdx "Inlining Arg"
;* V61 tmp56 [V61 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
;* V62 tmp57 [V62 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V63 tmp58 [V63 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V64 tmp59 [V64 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V65 tmp60 [V65 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V66 tmp61 [V66 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp"
;* V67 tmp62 [V67 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
;* V68 tmp63 [V68 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V69 tmp64 [V69 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return"
;* V70 tmp65 [V70 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp"
-; V71 tmp66 [V71,T12] ( 3, 6 ) long -> rax "Inlining Arg"
+; V71 tmp66 [V71,T12] ( 3, 6 ) long -> rdx "Inlining Arg"
;* V72 tmp67 [V72 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
;* V73 tmp68 [V73 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V74 tmp69 [V74 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V75 tmp70 [V75 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V76 tmp71 [V76 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V77 tmp72 [V77 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp"
;* V78 tmp73 [V78 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
;* V79 tmp74 [V79 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V80 tmp75 [V80 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return"
;* V81 tmp76 [V81 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp"
-; V82 tmp77 [V82,T13] ( 3, 6 ) long -> rax "Inlining Arg"
+; V82 tmp77 [V82,T13] ( 3, 6 ) long -> rdx "Inlining Arg"
;* V83 tmp78 [V83 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
;* V84 tmp79 [V84 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V85 tmp80 [V85 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V86 tmp81 [V86 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V87 tmp82 [V87 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V88 tmp83 [V88 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp"
;* V89 tmp84 [V89 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
;* V90 tmp85 [V90 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V91 tmp86 [V91 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return"
;* V92 tmp87 [V92 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp"
-; V93 tmp88 [V93,T04] ( 6, 12 ) long -> rax "Inlining Arg"
-; V94 tmp89 [V94,T16] ( 3, 3 ) long -> rax "Inlining Arg"
+; V93 tmp88 [V93,T04] ( 6, 12 ) long -> rdx "Inlining Arg"
+; V94 tmp89 [V94,T16] ( 3, 3 ) long -> rdx "Inlining Arg"
;* V95 tmp90 [V95 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
;* V96 tmp91 [V96 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V97 tmp92 [V97 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V98 tmp93 [V98 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V99 tmp94 [V99 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V100 tmp95 [V100 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp"
;* V101 tmp96 [V101 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
;* V102 tmp97 [V102 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V103 tmp98 [V103 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return"
;* V104 tmp99 [V104 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp"
-; V105 tmp100 [V105,T17] ( 3, 3 ) long -> rax "Inlining Arg"
+; V105 tmp100 [V105,T17] ( 3, 3 ) long -> rdx "Inlining Arg"
;* V106 tmp101 [V106 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
;* V107 tmp102 [V107 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V108 tmp103 [V108 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V109 tmp104 [V109 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V110 tmp105 [V110 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V111 tmp106 [V111 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp"
;* V112 tmp107 [V112 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
;* V113 tmp108 [V113 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V114 tmp109 [V114 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return"
;* V115 tmp110 [V115 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp"
-; V116 tmp111 [V116,T18] ( 3, 3 ) long -> rax "Inlining Arg"
+; V116 tmp111 [V116,T18] ( 3, 3 ) long -> rdx "Inlining Arg"
;* V117 tmp112 [V117 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
;* V118 tmp113 [V118 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V119 tmp114 [V119 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V120 tmp115 [V120 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V121 tmp116 [V121 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V122 tmp117 [V122 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp"
;* V123 tmp118 [V123 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
;* V124 tmp119 [V124 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V125 tmp120 [V125 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return"
;* V126 tmp121 [V126 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp"
-; V127 tmp122 [V127,T19] ( 3, 3 ) long -> rax "Inlining Arg"
+; V127 tmp122 [V127,T19] ( 3, 3 ) long -> rdx "Inlining Arg"
;* V128 tmp123 [V128 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
;* V129 tmp124 [V129 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V130 tmp125 [V130 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V131 tmp126 [V131 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V132 tmp127 [V132 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V133 tmp128 [V133 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp"
;* V134 tmp129 [V134 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
;* V135 tmp130 [V135 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V136 tmp131 [V136 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return"
;* V137 tmp132 [V137 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp"
-; V138 tmp133 [V138,T20] ( 3, 3 ) long -> rax "Inlining Arg"
+; V138 tmp133 [V138,T20] ( 3, 3 ) long -> rdx "Inlining Arg"
;* V139 tmp134 [V139 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
;* V140 tmp135 [V140 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V141 tmp136 [V141 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V142 tmp137 [V142 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V143 tmp138 [V143 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V144 tmp139 [V144 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp"
;* V145 tmp140 [V145 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
;* V146 tmp141 [V146 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V147 tmp142 [V147 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return"
;* V148 tmp143 [V148 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp"
-; V149 tmp144 [V149,T21] ( 3, 3 ) long -> rax "Inlining Arg"
+; V149 tmp144 [V149,T21] ( 3, 3 ) long -> rdx "Inlining Arg"
;* V150 tmp145 [V150 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
;* V151 tmp146 [V151 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V152 tmp147 [V152 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V153 tmp148 [V153 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V154 tmp149 [V154 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V155 tmp150 [V155 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp"
;* V156 tmp151 [V156 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
;* V157 tmp152 [V157 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V158 tmp153 [V158 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return"
;* V159 tmp154 [V159 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp"
-; V160 tmp155 [V160,T22] ( 3, 3 ) long -> rax "Inlining Arg"
+; V160 tmp155 [V160,T22] ( 3, 3 ) long -> rdx "Inlining Arg"
;* V161 tmp156 [V161 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
;* V162 tmp157 [V162 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V163 tmp158 [V163 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V164 tmp159 [V164 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V165 tmp160 [V165 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V166 tmp161 [V166 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp"
;* V167 tmp162 [V167 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
;* V168 tmp163 [V168 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V169 tmp164 [V169 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return"
;* V170 tmp165 [V170 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp"
-; V171 tmp166 [V171,T14] ( 3, 6 ) long -> rax "Inlining Arg"
+; V171 tmp166 [V171,T14] ( 3, 6 ) long -> rdx "Inlining Arg"
;* V172 tmp167 [V172 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
;* V173 tmp168 [V173 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V174 tmp169 [V174 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V175 tmp170 [V175 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V176 tmp171 [V176 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V177 tmp172 [V177 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp"
;* V178 tmp173 [V178 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
;* V179 tmp174 [V179 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V180 tmp175 [V180 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return"
;* V181 tmp176 [V181 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp"
-; V182 tmp177 [V182,T05] ( 6, 12 ) long -> rax "Inlining Arg"
+; V182 tmp177 [V182,T05] ( 6, 12 ) long -> rcx "Inlining Arg"
;* V183 tmp178 [V183 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V14.Item1 (fldOffset=0x0)" P-DEP
;* V184 tmp179 [V184 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V14.Item2 (fldOffset=0x8)" P-DEP
-; V185 tmp180 [V185,T23] ( 2, 2 ) long -> rax "field V15.Item1 (fldOffset=0x0)" P-INDEP
-; V186 tmp181 [V186,T24] ( 2, 2 ) long -> rdx "field V15.Item2 (fldOffset=0x8)" P-INDEP
+; V185 tmp180 [V185,T23] ( 2, 2 ) long -> rdx "field V15.Item1 (fldOffset=0x0)" P-INDEP
+; V186 tmp181 [V186,T24] ( 2, 2 ) long -> rcx "field V15.Item2 (fldOffset=0x8)" P-INDEP
;* V187 tmp182 [V187 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V25.Item1 (fldOffset=0x0)" P-DEP
;* V188 tmp183 [V188 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V25.Item2 (fldOffset=0x8)" P-DEP
-; V189 tmp184 [V189,T25] ( 2, 2 ) long -> rax "field V26.Item1 (fldOffset=0x0)" P-INDEP
-; V190 tmp185 [V190,T26] ( 2, 2 ) long -> rdx "field V26.Item2 (fldOffset=0x8)" P-INDEP
+; V189 tmp184 [V189,T25] ( 2, 2 ) long -> rdx "field V26.Item1 (fldOffset=0x0)" P-INDEP
+; V190 tmp185 [V190,T26] ( 2, 2 ) long -> rcx "field V26.Item2 (fldOffset=0x8)" P-INDEP
;* V191 tmp186 [V191 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V36.Item1 (fldOffset=0x0)" P-DEP
;* V192 tmp187 [V192 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V36.Item2 (fldOffset=0x8)" P-DEP
-; V193 tmp188 [V193,T27] ( 2, 2 ) long -> rax "field V37.Item1 (fldOffset=0x0)" P-INDEP
-; V194 tmp189 [V194,T28] ( 2, 2 ) long -> rdx "field V37.Item2 (fldOffset=0x8)" P-INDEP
+; V193 tmp188 [V193,T27] ( 2, 2 ) long -> rdx "field V37.Item1 (fldOffset=0x0)" P-INDEP
+; V194 tmp189 [V194,T28] ( 2, 2 ) long -> rcx "field V37.Item2 (fldOffset=0x8)" P-INDEP
;* V195 tmp190 [V195 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V47.Item1 (fldOffset=0x0)" P-DEP
;* V196 tmp191 [V196 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V47.Item2 (fldOffset=0x8)" P-DEP
-; V197 tmp192 [V197,T29] ( 2, 2 ) long -> rax "field V48.Item1 (fldOffset=0x0)" P-INDEP
-; V198 tmp193 [V198,T30] ( 2, 2 ) long -> rdx "field V48.Item2 (fldOffset=0x8)" P-INDEP
+; V197 tmp192 [V197,T29] ( 2, 2 ) long -> rdx "field V48.Item1 (fldOffset=0x0)" P-INDEP
+; V198 tmp193 [V198,T30] ( 2, 2 ) long -> rcx "field V48.Item2 (fldOffset=0x8)" P-INDEP
;* V199 tmp194 [V199 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V58.Item1 (fldOffset=0x0)" P-DEP
;* V200 tmp195 [V200 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V58.Item2 (fldOffset=0x8)" P-DEP
-; V201 tmp196 [V201,T31] ( 2, 2 ) long -> rax "field V59.Item1 (fldOffset=0x0)" P-INDEP
-; V202 tmp197 [V202,T32] ( 2, 2 ) long -> rdx "field V59.Item2 (fldOffset=0x8)" P-INDEP
+; V201 tmp196 [V201,T31] ( 2, 2 ) long -> rdx "field V59.Item1 (fldOffset=0x0)" P-INDEP
+; V202 tmp197 [V202,T32] ( 2, 2 ) long -> rcx "field V59.Item2 (fldOffset=0x8)" P-INDEP
;* V203 tmp198 [V203 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V69.Item1 (fldOffset=0x0)" P-DEP
;* V204 tmp199 [V204 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V69.Item2 (fldOffset=0x8)" P-DEP
-; V205 tmp200 [V205,T33] ( 2, 2 ) long -> rax "field V70.Item1 (fldOffset=0x0)" P-INDEP
-; V206 tmp201 [V206,T34] ( 2, 2 ) long -> rdx "field V70.Item2 (fldOffset=0x8)" P-INDEP
+; V205 tmp200 [V205,T33] ( 2, 2 ) long -> rdx "field V70.Item1 (fldOffset=0x0)" P-INDEP
+; V206 tmp201 [V206,T34] ( 2, 2 ) long -> rcx "field V70.Item2 (fldOffset=0x8)" P-INDEP
;* V207 tmp202 [V207 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V80.Item1 (fldOffset=0x0)" P-DEP
;* V208 tmp203 [V208 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V80.Item2 (fldOffset=0x8)" P-DEP
-; V209 tmp204 [V209,T35] ( 2, 2 ) long -> rax "field V81.Item1 (fldOffset=0x0)" P-INDEP
-; V210 tmp205 [V210,T36] ( 2, 2 ) long -> rdx "field V81.Item2 (fldOffset=0x8)" P-INDEP
+; V209 tmp204 [V209,T35] ( 2, 2 ) long -> rdx "field V81.Item1 (fldOffset=0x0)" P-INDEP
+; V210 tmp205 [V210,T36] ( 2, 2 ) long -> rcx "field V81.Item2 (fldOffset=0x8)" P-INDEP
;* V211 tmp206 [V211 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V91.Item1 (fldOffset=0x0)" P-DEP
;* V212 tmp207 [V212 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V91.Item2 (fldOffset=0x8)" P-DEP
-; V213 tmp208 [V213,T37] ( 2, 2 ) long -> rax "field V92.Item1 (fldOffset=0x0)" P-INDEP
-; V214 tmp209 [V214,T38] ( 2, 2 ) long -> rdx "field V92.Item2 (fldOffset=0x8)" P-INDEP
+; V213 tmp208 [V213,T37] ( 2, 2 ) long -> rdx "field V92.Item1 (fldOffset=0x0)" P-INDEP
+; V214 tmp209 [V214,T38] ( 2, 2 ) long -> rcx "field V92.Item2 (fldOffset=0x8)" P-INDEP
;* V215 tmp210 [V215 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V103.Item1 (fldOffset=0x0)" P-DEP
;* V216 tmp211 [V216 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V103.Item2 (fldOffset=0x8)" P-DEP
-; V217 tmp212 [V217,T41] ( 2, 1 ) long -> rax "field V104.Item1 (fldOffset=0x0)" P-INDEP
-; V218 tmp213 [V218,T42] ( 2, 1 ) long -> rdx "field V104.Item2 (fldOffset=0x8)" P-INDEP
+; V217 tmp212 [V217,T41] ( 2, 1 ) long -> rdx "field V104.Item1 (fldOffset=0x0)" P-INDEP
+; V218 tmp213 [V218,T42] ( 2, 1 ) long -> rcx "field V104.Item2 (fldOffset=0x8)" P-INDEP
;* V219 tmp214 [V219 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V114.Item1 (fldOffset=0x0)" P-DEP
;* V220 tmp215 [V220 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V114.Item2 (fldOffset=0x8)" P-DEP
-; V221 tmp216 [V221,T43] ( 2, 1 ) long -> rax "field V115.Item1 (fldOffset=0x0)" P-INDEP
-; V222 tmp217 [V222,T44] ( 2, 1 ) long -> rdx "field V115.Item2 (fldOffset=0x8)" P-INDEP
+; V221 tmp216 [V221,T43] ( 2, 1 ) long -> rdx "field V115.Item1 (fldOffset=0x0)" P-INDEP
+; V222 tmp217 [V222,T44] ( 2, 1 ) long -> rcx "field V115.Item2 (fldOffset=0x8)" P-INDEP
;* V223 tmp218 [V223 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V125.Item1 (fldOffset=0x0)" P-DEP
;* V224 tmp219 [V224 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V125.Item2 (fldOffset=0x8)" P-DEP
-; V225 tmp220 [V225,T45] ( 2, 1 ) long -> rax "field V126.Item1 (fldOffset=0x0)" P-INDEP
-; V226 tmp221 [V226,T46] ( 2, 1 ) long -> rdx "field V126.Item2 (fldOffset=0x8)" P-INDEP
+; V225 tmp220 [V225,T45] ( 2, 1 ) long -> rdx "field V126.Item1 (fldOffset=0x0)" P-INDEP
+; V226 tmp221 [V226,T46] ( 2, 1 ) long -> rcx "field V126.Item2 (fldOffset=0x8)" P-INDEP
;* V227 tmp222 [V227 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V136.Item1 (fldOffset=0x0)" P-DEP
;* V228 tmp223 [V228 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V136.Item2 (fldOffset=0x8)" P-DEP
-; V229 tmp224 [V229,T47] ( 2, 1 ) long -> rax "field V137.Item1 (fldOffset=0x0)" P-INDEP
-; V230 tmp225 [V230,T48] ( 2, 1 ) long -> rdx "field V137.Item2 (fldOffset=0x8)" P-INDEP
+; V229 tmp224 [V229,T47] ( 2, 1 ) long -> rdx "field V137.Item1 (fldOffset=0x0)" P-INDEP
+; V230 tmp225 [V230,T48] ( 2, 1 ) long -> rcx "field V137.Item2 (fldOffset=0x8)" P-INDEP
;* V231 tmp226 [V231 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V147.Item1 (fldOffset=0x0)" P-DEP
;* V232 tmp227 [V232 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V147.Item2 (fldOffset=0x8)" P-DEP
-; V233 tmp228 [V233,T49] ( 2, 1 ) long -> rax "field V148.Item1 (fldOffset=0x0)" P-INDEP
-; V234 tmp229 [V234,T50] ( 2, 1 ) long -> rdx "field V148.Item2 (fldOffset=0x8)" P-INDEP
+; V233 tmp228 [V233,T49] ( 2, 1 ) long -> rdx "field V148.Item1 (fldOffset=0x0)" P-INDEP
+; V234 tmp229 [V234,T50] ( 2, 1 ) long -> rcx "field V148.Item2 (fldOffset=0x8)" P-INDEP
;* V235 tmp230 [V235 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V158.Item1 (fldOffset=0x0)" P-DEP
;* V236 tmp231 [V236 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V158.Item2 (fldOffset=0x8)" P-DEP
-; V237 tmp232 [V237,T51] ( 2, 1 ) long -> rax "field V159.Item1 (fldOffset=0x0)" P-INDEP
-; V238 tmp233 [V238,T52] ( 2, 1 ) long -> rdx "field V159.Item2 (fldOffset=0x8)" P-INDEP
+; V237 tmp232 [V237,T51] ( 2, 1 ) long -> rdx "field V159.Item1 (fldOffset=0x0)" P-INDEP
+; V238 tmp233 [V238,T52] ( 2, 1 ) long -> rcx "field V159.Item2 (fldOffset=0x8)" P-INDEP
;* V239 tmp234 [V239 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V169.Item1 (fldOffset=0x0)" P-DEP
;* V240 tmp235 [V240 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V169.Item2 (fldOffset=0x8)" P-DEP
-; V241 tmp236 [V241,T53] ( 2, 1 ) long -> rax "field V170.Item1 (fldOffset=0x0)" P-INDEP
-; V242 tmp237 [V242,T54] ( 2, 1 ) long -> rdx "field V170.Item2 (fldOffset=0x8)" P-INDEP
+; V241 tmp236 [V241,T53] ( 2, 1 ) long -> rdx "field V170.Item1 (fldOffset=0x0)" P-INDEP
+; V242 tmp237 [V242,T54] ( 2, 1 ) long -> rcx "field V170.Item2 (fldOffset=0x8)" P-INDEP
;* V243 tmp238 [V243 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V180.Item1 (fldOffset=0x0)" P-DEP
;* V244 tmp239 [V244 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V180.Item2 (fldOffset=0x8)" P-DEP
-; V245 tmp240 [V245,T39] ( 2, 2 ) long -> rax "field V181.Item1 (fldOffset=0x0)" P-INDEP
+; V245 tmp240 [V245,T39] ( 2, 2 ) long -> rcx "field V181.Item1 (fldOffset=0x0)" P-INDEP
; V246 tmp241 [V246,T40] ( 2, 2 ) long -> rdx "field V181.Item2 (fldOffset=0x8)" P-INDEP
; V247 cse0 [V247,T03] ( 17, 13.50) long -> r8 "CSE #01: aggressive"
-; V248 rat0 [V248,T15] ( 3, 5.75) int -> rax "ReplaceWithLclVar is creating a new local variable"
+; V248 rat0 [V248,T15] ( 3, 5.75) int -> rdx "ReplaceWithLclVar is creating a new local variable"
;
; Lcl frame size = 16
G_M37356_IG01:
push rbp
sub rsp, 16
lea rbp, [rsp+0x10]
;; size=10 bbWeight=1 PerfScore 1.75
G_M37356_IG02:
- mov ecx, esi
- mov r8, 0xD1FFAB1E
- imul rcx, r8
- mov rax, 0xD1FFAB1E
- add rax, rdx
- xor rax, qword ptr [rdi]
+ mov eax, esi
+ mov rcx, 0xD1FFAB1E
+ imul rax, rcx
+ mov rcx, 0xD1FFAB1E
+ add rcx, rdx
+ xor rcx, qword ptr [rdi]
mov qword ptr [rbp-0x08], rdx
mov r8, rdx
neg r8
mov r9, 0xD1FFAB1E
add r9, r8
xor r9, qword ptr [rdi+0x08]
- mul rdx:rax, r9
- xor rax, rdx
- add rcx, rax
- lea rax, [rdi+0x10]
- mov rdx, 0xD1FFAB1E
+ mov rdx, rcx
+ mulx rcx, rdx, r9
+ xor rdx, rcx
+ add rax, rdx
+ lea rdx, [rdi+0x10]
+ mov rcx, 0xD1FFAB1E
mov r9, qword ptr [rbp-0x08]
- add rdx, r9
- xor rdx, qword ptr [rax]
+ add rcx, r9
+ xor rcx, qword ptr [rdx]
mov r10, 0xD1FFAB1E
add r10, r8
- xor r10, qword ptr [rax+0x08]
- mov rax, r10
- mul rdx:rax, rdx
- xor rax, rdx
- add rax, rcx
- mov rcx, rax
- lea rax, [rdi+0x20]
- mov rdx, 0xD1FFAB1E
- add rdx, r9
- xor rdx, qword ptr [rax]
+ xor r10, qword ptr [rdx+0x08]
+ mov rdx, rcx
+ mulx rcx, rdx, r10
+ xor rdx, rcx
+ add rdx, rax
+ mov rax, rdx
+ lea rdx, [rdi+0x20]
+ mov rcx, 0xD1FFAB1E
+ add rcx, r9
+ xor rcx, qword ptr [rdx]
mov r10, 0xD1FFAB1E
add r10, r8
- xor r10, qword ptr [rax+0x08]
- mov rax, r10
- mul rdx:rax, rdx
- xor rax, rdx
- add rax, rcx
- mov rcx, rax
- lea rax, [rdi+0x30]
- mov rdx, 0xD1FFAB1E
- add rdx, r9
- xor rdx, qword ptr [rax]
+ xor r10, qword ptr [rdx+0x08]
+ mov rdx, rcx
+ mulx rcx, rdx, r10
+ xor rdx, rcx
+ add rdx, rax
+ mov rax, rdx
+ lea rdx, [rdi+0x30]
+ mov rcx, 0xD1FFAB1E
+ add rcx, r9
+ xor rcx, qword ptr [rdx]
mov r10, 0xD1FFAB1E
add r10, r8
- xor r10, qword ptr [rax+0x08]
- mov rax, r10
- mul rdx:rax, rdx
- xor rax, rdx
- add rax, rcx
- mov rcx, rax
- lea rax, [rdi+0x40]
- mov rdx, 0xD1FFAB1E
- add rdx, r9
- xor rdx, qword ptr [rax]
+ xor r10, qword ptr [rdx+0x08]
+ mov rdx, rcx
+ mulx rcx, rdx, r10
+ xor rdx, rcx
+ add rdx, rax
+ mov rax, rdx
+ lea rdx, [rdi+0x40]
+ mov rcx, 0xD1FFAB1E
+ add rcx, r9
+ xor rcx, qword ptr [rdx]
mov r10, 0xD1FFAB1E
add r10, r8
- xor r10, qword ptr [rax+0x08]
- mov rax, r10
- mul rdx:rax, rdx
- xor rax, rdx
- add rax, rcx
- mov rcx, rax
- lea rax, [rdi+0x50]
- mov rdx, 0xD1FFAB1E
- add rdx, r9
- ;; size=297 bbWeight=1 PerfScore 52.50
+ xor r10, qword ptr [rdx+0x08]
+ mov rdx, rcx
+ mulx rcx, rdx, r10
+ xor rdx, rcx
+ add rdx, rax
+ mov rax, rdx
+ lea rdx, [rdi+0x50]
+ ;; size=297 bbWeight=1 PerfScore 52.25
G_M37356_IG03:
- xor rdx, qword ptr [rax]
+ mov rcx, 0xD1FFAB1E
+ add rcx, r9
+ xor rcx, qword ptr [rdx]
mov r10, 0xD1FFAB1E
add r10, r8
- xor r10, qword ptr [rax+0x08]
- mov rax, r10
- mul rdx:rax, rdx
+ xor r10, qword ptr [rdx+0x08]
+ mov rdx, rcx
+ mulx rcx, rdx, r10
+ xor rdx, rcx
+ add rdx, rax
+ mov rax, rdx
+ lea rdx, [rdi+0x60]
+ mov rcx, 0xD1FFAB1E
+ add rcx, r9
+ xor rcx, qword ptr [rdx]
+ mov r10, 0xD1FFAB1E
+ add r10, r8
+ xor r10, qword ptr [rdx+0x08]
+ mov rdx, rcx
+ mulx rcx, rdx, r10
+ xor rdx, rcx
+ add rdx, rax
+ mov rax, rdx
+ lea rdx, [rdi+0x70]
+ mov rcx, 0xD1FFAB1E
+ add rcx, r9
+ xor rcx, qword ptr [rdx]
+ mov r10, 0xD1FFAB1E
+ add r10, r8
+ xor r10, qword ptr [rdx+0x08]
+ mov rdx, rcx
+ mulx rcx, rdx, r10
+ xor rdx, rcx
+ add rdx, rax
+ mov rax, rdx
+ shr rax, 37
xor rax, rdx
- add rax, rcx
- mov rcx, rax
- lea rax, [rdi+0x60]
mov rdx, 0xD1FFAB1E
- add rdx, r9
- xor rdx, qword ptr [rax]
- mov r10, 0xD1FFAB1E
- add r10, r8
- xor r10, qword ptr [rax+0x08]
- mov rax, r10
- mul rdx:rax, rdx
+ imul rdx, rax
+ mov rax, rdx
+ shr rax, 32
xor rax, rdx
- add rax, rcx
- mov rcx, rax
- lea rax, [rdi+0x70]
- mov rdx, 0xD1FFAB1E
- add rdx, r9
- xor rdx, qword ptr [rax]
- mov r10, 0xD1FFAB1E
- add r10, r8
- xor r10, qword ptr [rax+0x08]
- mov rax, r10
- mul rdx:rax, rdx
- xor rax, rdx
- add rax, rcx
- mov rcx, rax
- shr rcx, 37
- xor rcx, rax
- mov rax, 0xD1FFAB1E
- imul rax, rcx
- mov rcx, rax
- shr rcx, 32
- xor rcx, rax
- lea eax, [rsi-0x80]
- shr eax, 4
- cmp eax, 6
+ lea edx, [rsi-0x80]
+ shr edx, 4
+ cmp edx, 6
ja SHORT G_M37356_IG05
- ;; size=181 bbWeight=1 PerfScore 33.75
+ ;; size=200 bbWeight=1 PerfScore 34.25
G_M37356_IG04:
- mov eax, eax
- lea rdx, [reloc @RWD00]
- mov edx, dword ptr [rdx+4*rax]
+ mov edx, edx
+ lea rcx, [reloc @RWD00]
+ mov ecx, dword ptr [rcx+4*rdx]
lea r10, G_M37356_IG02
- add rdx, r10
- jmp rdx
+ add rcx, r10
+ jmp rcx
;; size=24 bbWeight=0.88 PerfScore 5.25
G_M37356_IG05:
- lea rax, [rdi+0xE0]
- mov rdx, 0xD1FFAB1E
- add rdx, r9
- xor rdx, qword ptr [rax]
+ lea rdx, [rdi+0xE0]
+ mov rcx, 0xD1FFAB1E
+ add rcx, r9
+ xor rcx, qword ptr [rdx]
mov r10, 0xD1FFAB1E
add r10, r8
- xor r10, qword ptr [rax+0x08]
- mov rax, r10
- mul rdx:rax, rdx
- xor rax, rdx
- add rax, rcx
- mov rcx, rax
- ;; size=55 bbWeight=0.50 PerfScore 4.75
+ xor r10, qword ptr [rdx+0x08]
+ mov rdx, rcx
+ mulx rcx, rdx, r10
+ xor rdx, rcx
+ add rdx, rax
+ mov rax, rdx
+ ;; size=57 bbWeight=0.50 PerfScore 4.75
G_M37356_IG06:
- lea rax, [rdi+0xD0]
- mov rdx, 0xD1FFAB1E
- add rdx, r9
- xor rdx, qword ptr [rax]
+ lea rdx, [rdi+0xD0]
+ mov rcx, 0xD1FFAB1E
+ add rcx, r9
+ xor rcx, qword ptr [rdx]
mov r10, 0xD1FFAB1E
add r10, r8
- xor r10, qword ptr [rax+0x08]
- mov rax, r10
- mul rdx:rax, rdx
- xor rax, rdx
- add rax, rcx
- mov rcx, rax
- ;; size=55 bbWeight=0.50 PerfScore 4.75
+ xor r10, qword ptr [rdx+0x08]
+ mov rdx, rcx
+ mulx rcx, rdx, r10
+ xor rdx, rcx
+ add rdx, rax
+ mov rax, rdx
+ ;; size=57 bbWeight=0.50 PerfScore 4.75
G_M37356_IG07:
- lea rax, [rdi+0xC0]
- mov rdx, 0xD1FFAB1E
- add rdx, r9
- xor rdx, qword ptr [rax]
+ lea rdx, [rdi+0xC0]
+ mov rcx, 0xD1FFAB1E
+ add rcx, r9
+ xor rcx, qword ptr [rdx]
mov r10, 0xD1FFAB1E
add r10, r8
- xor r10, qword ptr [rax+0x08]
- mov rax, r10
- mul rdx:rax, rdx
- xor rax, rdx
- add rax, rcx
- mov rcx, rax
- ;; size=55 bbWeight=0.50 PerfScore 4.75
+ xor r10, qword ptr [rdx+0x08]
+ mov rdx, rcx
+ mulx rcx, rdx, r10
+ xor rdx, rcx
+ add rdx, rax
+ mov rax, rdx
+ ;; size=57 bbWeight=0.50 PerfScore 4.75
G_M37356_IG08:
- lea rax, [rdi+0xB0]
- mov rdx, 0xD1FFAB1E
- add rdx, r9
- xor rdx, qword ptr [rax]
+ lea rdx, [rdi+0xB0]
+ mov rcx, 0xD1FFAB1E
+ add rcx, r9
+ xor rcx, qword ptr [rdx]
mov r10, 0xD1FFAB1E
add r10, r8
- xor r10, qword ptr [rax+0x08]
- mov rax, r10
- mul rdx:rax, rdx
- xor rax, rdx
- add rax, rcx
- mov rcx, rax
- ;; size=55 bbWeight=0.50 PerfScore 4.75
+ xor r10, qword ptr [rdx+0x08]
+ mov rdx, rcx
+ mulx rcx, rdx, r10
+ xor rdx, rcx
+ add rdx, rax
+ mov rax, rdx
+ ;; size=57 bbWeight=0.50 PerfScore 4.75
G_M37356_IG09:
- lea rax, [rdi+0xA0]
- mov rdx, 0xD1FFAB1E
- add rdx, r9
- xor rdx, qword ptr [rax]
+ lea rdx, [rdi+0xA0]
+ mov rcx, 0xD1FFAB1E
+ add rcx, r9
+ xor rcx, qword ptr [rdx]
mov r10, 0xD1FFAB1E
add r10, r8
- xor r10, qword ptr [rax+0x08]
- mov rax, r10
- mul rdx:rax, rdx
- xor rax, rdx
- add rax, rcx
- mov rcx, rax
- ;; size=55 bbWeight=0.50 PerfScore 4.75
+ xor r10, qword ptr [rdx+0x08]
+ mov rdx, rcx
+ mulx rcx, rdx, r10
+ xor rdx, rcx
+ add rdx, rax
+ mov rax, rdx
+ ;; size=57 bbWeight=0.50 PerfScore 4.75
G_M37356_IG10:
- lea rax, [rdi+0x90]
- mov rdx, 0xD1FFAB1E
- add rdx, r9
- xor rdx, qword ptr [rax]
+ lea rdx, [rdi+0x90]
+ mov rcx, 0xD1FFAB1E
+ add rcx, r9
+ xor rcx, qword ptr [rdx]
mov r10, 0xD1FFAB1E
add r10, r8
- xor r10, qword ptr [rax+0x08]
- mov rax, r10
- mul rdx:rax, rdx
- xor rax, rdx
- add rax, rcx
- mov rcx, rax
- ;; size=55 bbWeight=0.50 PerfScore 4.75
+ xor r10, qword ptr [rdx+0x08]
+ mov rdx, rcx
+ mulx rcx, rdx, r10
+ xor rdx, rcx
+ add rdx, rax
+ mov rax, rdx
+ ;; size=57 bbWeight=0.50 PerfScore 4.75
G_M37356_IG11:
- lea rax, [rdi+0x80]
- mov rdx, 0xD1FFAB1E
- add rdx, r9
- xor rdx, qword ptr [rax]
+ lea rdx, [rdi+0x80]
+ mov rcx, 0xD1FFAB1E
+ add rcx, r9
+ xor rcx, qword ptr [rdx]
mov r10, 0xD1FFAB1E
add r10, r8
- xor r10, qword ptr [rax+0x08]
- mov rax, r10
- mul rdx:rax, rdx
- xor rax, rdx
- add rax, rcx
- mov rcx, rax
- ;; size=55 bbWeight=0.50 PerfScore 4.75
+ xor r10, qword ptr [rdx+0x08]
+ mov rdx, rcx
+ mulx rcx, rdx, r10
+ xor rdx, rcx
+ add rdx, rax
+ mov rax, rdx
+ ;; size=57 bbWeight=0.50 PerfScore 4.75
G_M37356_IG12:
- mov eax, esi
- lea rax, [rdi+rax-0x10]
- mov rdx, 0xD1FFAB1E
- add rdx, r9
- xor rdx, qword ptr [rax]
+ mov edx, esi
+ lea rdx, [rdi+rdx-0x10]
+ mov rcx, 0xD1FFAB1E
+ add rcx, r9
+ xor rcx, qword ptr [rdx]
mov rdi, 0xD1FFAB1E
add rdi, r8
- xor rdi, qword ptr [rax+0x08]
- mov rax, rdi
- mul rdx:rax, rdx
- xor rax, rdx
- add rax, rcx
- mov rcx, rax
- shr rcx, 37
- xor rcx, rax
- mov rax, 0xD1FFAB1E
- imul rax, rcx
- mov rcx, rax
- shr rcx, 32
+ xor rdi, qword ptr [rdx+0x08]
+ mov rdx, rcx
+ mulx rdx, rcx, rdi
+ xor rcx, rdx
+ add rcx, rax
+ mov rax, rcx
+ shr rax, 37
xor rax, rcx
- ;; size=86 bbWeight=1 PerfScore 14.25
+ mov rcx, 0xD1FFAB1E
+ imul rcx, rax
+ mov rax, rcx
+ shr rax, 32
+ xor rax, rcx
+ ;; size=88 bbWeight=1 PerfScore 14.25
G_M37356_IG13:
add rsp, 16
pop rbp
ret
;; size=6 bbWeight=1 PerfScore 1.75
RWD00 dd G_M37356_IG12 - G_M37356_IG02
dd G_M37356_IG11 - G_M37356_IG02
dd G_M37356_IG10 - G_M37356_IG02
dd G_M37356_IG09 - G_M37356_IG02
dd G_M37356_IG08 - G_M37356_IG02
dd G_M37356_IG07 - G_M37356_IG02
dd G_M37356_IG06 - G_M37356_IG02
-; Total bytes of code 989, prolog size 10, PerfScore 142.50, instruction count 227, allocated bytes for code 989 (MethodHash=d8616e13) for method System.IO.Hashing.XxHash3:HashLength129To240(ptr,uint,ulong):ulong (FullOpts)
+; Total bytes of code 1024, prolog size 10, PerfScore 142.75, instruction count 228, allocated bytes for code 1024 (MethodHash=d8616e13) for method System.IO.Hashing.XxHash3:HashLength129To240(ptr,uint,ulong):ulong (FullOpts)
; ============================================================
```
20 (9.57 % of base) - System.IO.Hashing.XxHash128:HashLength9To16(ptr,uint,ulong):System.IO.Hashing.XxHash128+Hash128
```diff
; Assembly listing for method System.IO.Hashing.XxHash128:HashLength9To16(ptr,uint,ulong):System.IO.Hashing.XxHash128+Hash128 (FullOpts)
; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix
; FullOpts code
; optimized code
; rbp based frame
; partially interruptible
; No PGO data
; 0 inlinees with PGO data; 10 single block inlinees; 4 inlinees without PGO data
; Final local variable assignments
;
; V00 arg0 [V00,T01] ( 4, 4 ) long -> rdi single-def
; V01 arg1 [V01,T02] ( 4, 4 ) int -> rsi single-def
; V02 arg2 [V02,T03] ( 4, 4 ) long -> rdx single-def
; V03 loc0 [V03,T10] ( 2, 2 ) long -> rax
; V04 loc1 [V04,T11] ( 2, 2 ) long -> rcx
; V05 loc2 [V05,T00] ( 6, 6 ) long -> rdi
-; V06 loc3 [V06,T08] ( 3, 3 ) long -> [rbp-0x08] spill-single-def
-; V07 loc4 [V07,T12] ( 2, 2 ) long -> rax ld-addr-op
-; V08 loc5 [V08,T06] ( 5, 5 ) long -> rdx
-; V09 loc6 [V09,T13] ( 2, 2 ) long -> rax ld-addr-op
+; V06 loc3 [V06,T08] ( 3, 3 ) long -> rax
+; V07 loc4 [V07,T12] ( 2, 2 ) long -> rdx ld-addr-op
+; V08 loc5 [V08,T06] ( 5, 5 ) long -> [rbp-0x08]
+; V09 loc6 [V09,T13] ( 2, 2 ) long -> rcx ld-addr-op
;# V10 OutArgs [V10 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
; V11 tmp1 [V11,T07] ( 2, 4 ) long -> rdx "impAppendStmt"
;* V12 tmp2 [V12 ] ( 0, 0 ) long -> zero-ref
;* V13 tmp3 [V13 ] ( 0, 0 ) long -> zero-ref
;* V14 tmp4 [V14 ] ( 0, 0 ) long -> zero-ref
;* V15 tmp5 [V15 ] ( 0, 0 ) struct (16) zero-ref multireg-ret ld-addr-op "NewObj constructor temp"
;* V16 tmp6 [V16 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V17 tmp7 [V17 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V18 tmp8 [V18 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V19 tmp9 [V19 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V20 tmp10 [V20 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V21 tmp11 [V21 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return"
;* V22 tmp12 [V22 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp"
;* V23 tmp13 [V23 ] ( 0, 0 ) int -> zero-ref "Inlining Arg"
;* V24 tmp14 [V24 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V25 tmp15 [V25 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V26 tmp16 [V26 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return"
;* V27 tmp17 [V27 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp"
-; V28 tmp18 [V28,T04] ( 3, 6 ) long -> rax "Inlining Arg"
-; V29 tmp19 [V29,T05] ( 3, 6 ) long -> rdx "Inlining Arg"
+; V28 tmp18 [V28,T04] ( 3, 6 ) long -> rdx "Inlining Arg"
+; V29 tmp19 [V29,T05] ( 3, 6 ) long -> rax "Inlining Arg"
;* V30 tmp20 [V30 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V31 tmp21 [V31 ] ( 0, 0 ) long -> zero-ref "field V15.Low64 (fldOffset=0x0)" P-INDEP
;* V32 tmp22 [V32 ] ( 0, 0 ) long -> zero-ref "field V15.High64 (fldOffset=0x8)" P-INDEP
;* V33 tmp23 [V33 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V21.Item1 (fldOffset=0x0)" P-DEP
;* V34 tmp24 [V34 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V21.Item2 (fldOffset=0x8)" P-DEP
-; V35 tmp25 [V35,T14] ( 2, 2 ) long -> rax "field V22.Item1 (fldOffset=0x0)" P-INDEP
-; V36 tmp26 [V36,T15] ( 2, 2 ) long -> rdx "field V22.Item2 (fldOffset=0x8)" P-INDEP
+; V35 tmp25 [V35,T14] ( 2, 2 ) long -> rdx "field V22.Item1 (fldOffset=0x0)" P-INDEP
+; V36 tmp26 [V36,T15] ( 2, 2 ) long -> rax "field V22.Item2 (fldOffset=0x8)" P-INDEP
;* V37 tmp27 [V37 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V26.Item1 (fldOffset=0x0)" P-DEP
;* V38 tmp28 [V38 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V26.Item2 (fldOffset=0x8)" P-DEP
-; V39 tmp29 [V39,T09] ( 3, 3 ) long -> rax "field V27.Item1 (fldOffset=0x0)" P-INDEP
-; V40 tmp30 [V40,T16] ( 2, 2 ) long -> rdx "field V27.Item2 (fldOffset=0x8)" P-INDEP
+; V39 tmp29 [V39,T09] ( 3, 3 ) long -> rdx "field V27.Item1 (fldOffset=0x0)" P-INDEP
+; V40 tmp30 [V40,T16] ( 2, 2 ) long -> rcx "field V27.Item2 (fldOffset=0x8)" P-INDEP
;
; Lcl frame size = 16
G_M25789_IG01:
push rbp
sub rsp, 16
lea rbp, [rsp+0x10]
;; size=10 bbWeight=1 PerfScore 1.75
G_M25789_IG02:
mov rax, rdx
neg rax
mov rcx, 0xD1FFAB1E
add rax, rcx
mov rcx, 0xD1FFAB1E
add rcx, rdx
mov rdx, qword ptr [rdi]
mov r8d, esi
mov rdi, qword ptr [rdi+r8-0x08]
xor rdx, rdi
- xor rax, rdx
- mov rdx, 0xD1FFAB1E
- mul rdx:rax, rdx
+ xor rdx, rax
+ mov rax, 0xD1FFAB1E
+ mulx rax, rdx, rax
dec esi
shl rsi, 54
- add rax, rsi
+ add rdx, rsi
xor rdi, rcx
- add rdx, rdi
+ add rax, rdi
mov ecx, edi
mov edi, 0xD1FFAB1E
imul rcx, rdi
- add rdx, rcx
- mov qword ptr [rbp-0x08], rdx
- mov rcx, rdx
+ add rax, rcx
+ mov rcx, rax
bswap rcx
- xor rax, rcx
+ xor rdx, rcx
mov rcx, 0xD1FFAB1E
- mul rdx:rax, rcx
- imul rcx, qword ptr [rbp-0x08]
- add rdx, rcx
- mov rcx, rax
- shr rcx, 37
- xor rcx, rax
- mov rax, 0xD1FFAB1E
- imul rax, rcx
- mov rcx, rax
- shr rcx, 32
- xor rax, rcx
+ mulx rcx, rdx, rcx
+ mov rdi, 0xD1FFAB1E
+ imul rax, rdi
+ add rax, rcx
mov rcx, rdx
shr rcx, 37
xor rcx, rdx
mov rdx, 0xD1FFAB1E
imul rdx, rcx
mov rcx, rdx
shr rcx, 32
- xor rdx, rcx
- ;; size=193 bbWeight=1 PerfScore 32.25
+ xor rcx, rdx
+ mov rdx, rax
+ shr rdx, 37
+ xor rdx, rax
+ mov rax, 0xD1FFAB1E
+ imul rax, rdx
+ mov rdx, rax
+ shr rdx, 32
+ xor rax, rdx
+ mov qword ptr [rbp-0x08], rax
+ mov rax, rcx
+ mov rdx, qword ptr [rbp-0x08]
+ ;; size=213 bbWeight=1 PerfScore 31.75
G_M25789_IG03:
add rsp, 16
pop rbp
ret
;; size=6 bbWeight=1 PerfScore 1.75
-; Total bytes of code 209, prolog size 10, PerfScore 35.75, instruction count 52, allocated bytes for code 209 (MethodHash=aca99b42) for method System.IO.Hashing.XxHash128:HashLength9To16(ptr,uint,ulong):System.IO.Hashing.XxHash128+Hash128 (FullOpts)
+; Total bytes of code 229, prolog size 10, PerfScore 35.25, instruction count 55, allocated bytes for code 229 (MethodHash=aca99b42) for method System.IO.Hashing.XxHash128:HashLength9To16(ptr,uint,ulong):System.IO.Hashing.XxHash128+Hash128 (FullOpts)
; ============================================================
```
5 (21.74 % of base) - System.IO.Hashing.XxHashShared:Mix16Bytes(ptr,ulong,ulong,ulong):ulong
```diff
; Assembly listing for method System.IO.Hashing.XxHashShared:Mix16Bytes(ptr,ulong,ulong,ulong):ulong (FullOpts)
; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix
; FullOpts code
; optimized code
; rsp based frame
; partially interruptible
; No PGO data
; 0 inlinees with PGO data; 2 single block inlinees; 3 inlinees without PGO data
; Final local variable assignments
;
; V00 arg0 [V00,T00] ( 4, 4 ) long -> rdi single-def
; V01 arg1 [V01,T02] ( 3, 3 ) long -> rsi single-def
; V02 arg2 [V02,T03] ( 3, 3 ) long -> rdx single-def
; V03 arg3 [V03,T01] ( 4, 4 ) long -> rcx single-def
;# V04 OutArgs [V04 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;* V05 tmp1 [V05 ] ( 0, 0 ) long -> zero-ref "impAppendStmt"
;* V06 tmp2 [V06 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V07 tmp3 [V07 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V08 tmp4 [V08 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V09 tmp5 [V09 ] ( 0, 0 ) long -> zero-ref "Inlining Arg"
;* V10 tmp6 [V10 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp"
;* V11 tmp7 [V11 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp"
;* V12 tmp8 [V12 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp"
;* V13 tmp9 [V13 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return"
;* V14 tmp10 [V14 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp"
;* V15 tmp11 [V15 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V13.Item1 (fldOffset=0x0)" P-DEP
;* V16 tmp12 [V16 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V13.Item2 (fldOffset=0x8)" P-DEP
; V17 tmp13 [V17,T04] ( 2, 2 ) long -> rax "field V14.Item1 (fldOffset=0x0)" P-INDEP
-; V18 tmp14 [V18,T05] ( 2, 2 ) long -> rdx "field V14.Item2 (fldOffset=0x8)" P-INDEP
+; V18 tmp14 [V18,T05] ( 2, 2 ) long -> rcx "field V14.Item2 (fldOffset=0x8)" P-INDEP
;
; Lcl frame size = 0
G_M9319_IG01:
;; size=0 bbWeight=1 PerfScore 0.00
G_M9319_IG02:
add rsi, rcx
xor rsi, qword ptr [rdi]
sub rdx, rcx
xor rdx, qword ptr [rdi+0x08]
mov rax, rdx
- mul rdx:rax, rsi
- xor rax, rdx
- ;; size=22 bbWeight=1 PerfScore 8.00
+ mov rdx, rsi
+ mulx rcx, rax, rax
+ xor rax, rcx
+ ;; size=27 bbWeight=1 PerfScore 8.25
G_M9319_IG03:
ret
;; size=1 bbWeight=1 PerfScore 1.00
-; Total bytes of code 23, prolog size 0, PerfScore 9.00, instruction count 8, allocated bytes for code 23 (MethodHash=e8a4db98) for method System.IO.Hashing.XxHashShared:Mix16Bytes(ptr,ulong,ulong,ulong):ulong (FullOpts)
+; Total bytes of code 28, prolog size 0, PerfScore 9.25, instruction count 9, allocated bytes for code 28 (MethodHash=e8a4db98) for method System.IO.Hashing.XxHashShared:Mix16Bytes(ptr,ulong,ulong,ulong):ulong (FullOpts)
; ============================================================
```
Note: some changes were skipped as they were too large to fit into a comment.