## Top method improvements
-64 (-28.44 % of base) - System.Decimal+DecCalc:VarDecCmpSub(byref,byref):int ```diff ; Assembly listing for method System.Decimal+DecCalc:VarDecCmpSub(byref,byref):int (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rbp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 6 single block inlinees; 1 inlinees without PGO data ; Final local variable assignments ; ; V00 arg0 [V00,T09] ( 5, 5 ) byref -> rdi single-def ; V01 arg1 [V01,T10] ( 5, 5 ) byref -> rsi single-def -; V02 loc0 [V02,T13] ( 7, 4.50) int -> [rbp-0x04] -; V03 loc1 [V03,T12] ( 8, 5.25) int -> rax +; V02 loc0 [V02,T13] ( 7, 4.50) int -> rax +; V03 loc1 [V03,T12] ( 8, 5.25) int -> rdx ; V04 loc2 [V04,T04] ( 7, 11 ) long -> registers ld-addr-op ; V05 loc3 [V05,T05] ( 7, 11 ) int -> registers ; V06 loc4 [V06,T14] ( 4, 2.50) long -> registers ; V07 loc5 [V07,T15] ( 4, 2.50) int -> registers -; V08 loc6 [V08,T18] ( 3, 1.50) int -> rax -; V09 loc7 [V09,T19] ( 3, 1.50) long -> rax +; V08 loc6 [V08,T18] ( 3, 1.50) int -> rdx +; V09 loc7 [V09,T19] ( 3, 1.50) long -> rdx ;* V10 loc8 [V10 ] ( 0, 0 ) int -> zero-ref ; V11 loc9 [V11,T02] ( 3, 12 ) long -> rdi ;* V12 loc10 [V12 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;# V13 OutArgs [V13 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" -; V14 tmp1 [V14,T11] ( 3, 6 ) int -> rax "dup spill" -; V15 tmp2 [V15,T06] ( 3, 8 ) int -> rax +; V14 tmp1 [V14,T11] ( 3, 6 ) int -> rdx "dup spill" +; V15 tmp2 [V15,T06] ( 3, 8 ) int -> rdx ; V16 tmp3 [V16,T01] ( 2, 16 ) int -> r9 "dup spill" ; V17 tmp4 [V17,T16] ( 2, 2 ) long -> rcx "impAppendStmt" ; V18 tmp5 [V18,T17] ( 2, 2 ) int -> rdi "impSpillLclRefs" ;* V19 tmp6 [V19 ] ( 0, 0 ) struct (16) zero-ref "ReadOnlySpan for CreateSpan" ;* V20 tmp7 [V20 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V21 tmp8 [V21 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V22 tmp9 [V22 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V23 tmp10 [V23 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V24 tmp11 [V24 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V25 tmp12 [V25 ] ( 0, 0 ) byref -> zero-ref "field V12._reference (fldOffset=0x0)" P-INDEP ;* V26 tmp13 [V26 ] ( 0, 0 ) int -> zero-ref "field V12._length (fldOffset=0x8)" P-INDEP ;* V27 tmp14 [V27 ] ( 0, 0 ) byref -> zero-ref "field V19._reference (fldOffset=0x0)" P-INDEP ;* V28 tmp15 [V28 ] ( 0, 0 ) int -> zero-ref "field V19._length (fldOffset=0x8)" P-INDEP ;* V29 tmp16 [V29 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V23.Item1 (fldOffset=0x0)" P-DEP ;* V30 tmp17 [V30 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V23.Item2 (fldOffset=0x8)" P-DEP ; V31 tmp18 [V31,T07] ( 2, 8 ) long -> rcx "field V24.Item1 (fldOffset=0x0)" P-INDEP ; V32 tmp19 [V32,T08] ( 2, 8 ) long -> rdx "field V24.Item2 (fldOffset=0x8)" P-INDEP ; V33 cse0 [V33,T03] ( 3, 12 ) long -> r10 "CSE #01: aggressive" ; V34 rat0 [V34,T00] ( 6, 18.75) long -> r9 "Widened IV V03" ; -; Lcl frame size = 16 +; Lcl frame size = 0 G_M9821_IG01: push rbp - sub rsp, 16 - lea rbp, [rsp+0x10] - ;; size=10 bbWeight=1 PerfScore 1.75 + mov rbp, rsp + ;; size=4 bbWeight=1 PerfScore 1.25 G_M9821_IG02: - mov eax, dword ptr [rsi] - mov edx, eax - sar edx, 31 - or edx, 1 - sub eax, dword ptr [rdi] + mov edx, dword ptr [rsi] + mov eax, edx + sar eax, 31 + or eax, 1 + sub edx, dword ptr [rdi] mov rcx, qword ptr [rdi+0x08] mov edi, dword ptr [rdi+0x04] mov r8, qword ptr [rsi+0x08] mov esi, dword ptr [rsi+0x04] - test eax, eax - jne SHORT G_M9821_IG06 + test edx, edx + je SHORT G_M9821_IG09 ;; size=30 bbWeight=1 PerfScore 14.25 G_M9821_IG03: - mov dword ptr [rbp-0x04], edx - ;; size=3 bbWeight=0.50 PerfScore 0.50 -G_M9821_IG04: - mov eax, edi - sub eax, esi - je G_M9821_IG13 - cmp eax, edi - jbe G_M9821_IG16 - ;; size=18 bbWeight=0.50 PerfScore 1.38 -G_M9821_IG05: - mov edx, dword ptr [rbp-0x04] + sar edx, 16 + jns SHORT G_M9821_IG04 neg edx - jmp G_M9821_IG18 - ;; size=10 bbWeight=0.50 PerfScore 1.62 -G_M9821_IG06: - sar eax, 16 - jns SHORT G_M9821_IG07 neg eax - neg edx - mov dword ptr [rbp-0x04], edx mov r9, rcx mov rcx, r8 mov r8, r9 mov r9d, esi mov esi, edi mov edi, r9d - mov edx, dword ptr [rbp-0x04] - ;; size=32 bbWeight=0.50 PerfScore 2.75 + ;; size=26 bbWeight=0.50 PerfScore 1.75 +G_M9821_IG04: + mov r9d, edx + align [0 bytes for IG05] + ;; size=3 bbWeight=0.75 PerfScore 0.19 +G_M9821_IG05: + cmp r9d, 9 + jb SHORT G_M9821_IG07 + ;; size=6 bbWeight=4 PerfScore 5.00 +G_M9821_IG06: + mov edx, 0xD1FFAB1E + jmp SHORT G_M9821_IG08 + ;; size=7 bbWeight=2 PerfScore 4.50 G_M9821_IG07: - mov r9d, eax - jmp SHORT G_M9821_IG11 - ;; size=5 bbWeight=0.75 PerfScore 1.69 + mov rdx, 0xD1FFAB1E ; static handle + mov edx, dword ptr [rdx+4*r9] + ;; size=14 bbWeight=2 PerfScore 4.50 G_M9821_IG08: - mov rax, 0xD1FFAB1E ; static handle - mov eax, dword ptr [rax+4*r9] - mov dword ptr [rbp-0x04], edx - ;; size=17 bbWeight=2 PerfScore 6.50 -G_M9821_IG09: - mov r10d, eax - mov rax, r10 - mul rdx:rax, rcx - mov rcx, rax + mov r10d, edx + mov rdx, r10 + mulx rdx, rcx, rcx mov edi, edi imul rdi, r10 add rdi, rdx - mov rax, rdi - shr rax, 32 - jne SHORT G_M9821_IG17 + mov rdx, rdi + shr rdx, 32 + jne SHORT G_M9821_IG13 add r9d, -9 test r9d, r9d - jle SHORT G_M9821_IG04 - ;; size=39 bbWeight=4 PerfScore 38.00 + jg SHORT G_M9821_IG05 + ;; size=38 bbWeight=4 PerfScore 37.00 +G_M9821_IG09: + mov edx, edi + sub edx, esi + jne SHORT G_M9821_IG11 + mov rdx, rcx + sub rdx, r8 + je SHORT G_M9821_IG10 + cmp rdx, rcx + jbe SHORT G_M9821_IG13 + jmp SHORT G_M9821_IG12 + ;; size=21 bbWeight=0.50 PerfScore 3.12 G_M9821_IG10: - mov edx, dword ptr [rbp-0x04] - ;; size=3 bbWeight=2 PerfScore 2.00 -G_M9821_IG11: - cmp r9d, 9 - jb SHORT G_M9821_IG08 - ;; size=6 bbWeight=4 PerfScore 5.00 -G_M9821_IG12: - mov eax, 0xD1FFAB1E - mov dword ptr [rbp-0x04], edx - jmp SHORT G_M9821_IG09 - ;; size=10 bbWeight=2 PerfScore 6.50 -G_M9821_IG13: - mov rax, rcx - sub rax, r8 - je SHORT G_M9821_IG15 - cmp rax, rcx - ja G_M9821_IG05 - ;; size=17 bbWeight=0.50 PerfScore 1.38 -G_M9821_IG14: - mov edx, dword ptr [rbp-0x04] - jmp SHORT G_M9821_IG18 - ;; size=5 bbWeight=0.25 PerfScore 0.75 -G_M9821_IG15: - xor edx, edx - jmp SHORT G_M9821_IG18 + xor eax, eax + jmp SHORT G_M9821_IG13 ;; size=4 bbWeight=0.50 PerfScore 1.12 -G_M9821_IG16: - mov edx, dword ptr [rbp-0x04] - jmp SHORT G_M9821_IG18 - ;; size=5 bbWeight=0.25 PerfScore 0.75 -G_M9821_IG17: - mov edx, dword ptr [rbp-0x04] - ;; size=3 bbWeight=2 PerfScore 2.00 -G_M9821_IG18: - mov eax, edx - ;; size=2 bbWeight=1 PerfScore 0.25 -G_M9821_IG19: - add rsp, 16 +G_M9821_IG11: + cmp edx, edi + jbe SHORT G_M9821_IG13 + ;; size=4 bbWeight=0.50 PerfScore 0.62 +G_M9821_IG12: + neg eax + ;; size=2 bbWeight=0.50 PerfScore 0.12 +G_M9821_IG13: pop rbp ret - ;; size=6 bbWeight=1 PerfScore 1.75 + ;; size=2 bbWeight=1 PerfScore 1.50 -; Total bytes of code 225, prolog size 10, PerfScore 89.94, instruction count 75, allocated bytes for code 225 (MethodHash=418ad9a2) for method System.Decimal+DecCalc:VarDecCmpSub(byref,byref):int (FullOpts) +; Total bytes of code 161, prolog size 4, PerfScore 74.94, instruction count 59, allocated bytes for code 161 (MethodHash=418ad9a2) for method System.Decimal+DecCalc:VarDecCmpSub(byref,byref):int (FullOpts) ; ============================================================ ```
-42 (-6.92 % of base) - System.Numerics.BigIntegerCalculator:MulAdd1(System.Span`1[nuint],System.ReadOnlySpan`1[nuint],nuint):nuint ```diff ; Assembly listing for method System.Numerics.BigIntegerCalculator:MulAdd1(System.Span`1[nuint],System.ReadOnlySpan`1[nuint],nuint):nuint (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rbp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 95 single block inlinees; 10 inlinees without PGO data ; Final local variable assignments ; ;* V00 arg0 [V00 ] ( 0, 0 ) struct (16) zero-ref multireg-arg ld-addr-op single-def ;* V01 arg1 [V01 ] ( 0, 0 ) struct (16) zero-ref multireg-arg ld-addr-op single-def ; V02 arg2 [V02,T02] ( 8, 22 ) long -> r8 single-def -; V03 loc0 [V03,T04] ( 7, 21 ) int -> r9 -; V04 loc1 [V04,T00] ( 24, 53.91) int -> r10 -; V05 loc2 [V05,T06] ( 8, 18 ) long -> [rbp-0x18] +; V03 loc0 [V03,T04] ( 7, 21 ) int -> rax +; V04 loc1 [V04,T00] ( 24, 53.91) int -> r9 +; V05 loc2 [V05,T06] ( 8, 18 ) long -> r10 ;* V06 loc3 [V06 ] ( 0, 0 ) struct (16) zero-ref ;* V07 loc4 [V07 ] ( 0, 0 ) struct (16) zero-ref ;* V08 loc5 [V08 ] ( 0, 0 ) struct (16) zero-ref ;* V09 loc6 [V09 ] ( 0, 0 ) struct (16) zero-ref ;* V10 loc7 [V10 ] ( 0, 0 ) struct (16) zero-ref ;# V11 OutArgs [V11 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ;* V12 tmp1 [V12 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V13 tmp2 [V13 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V14 tmp3 [V14 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V15 tmp4 [V15 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V16 tmp5 [V16 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V17 tmp6 [V17 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V18 tmp7 [V18 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V19 tmp8 [V19 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V20 tmp9 [V20 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V21 tmp10 [V21 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V22 tmp11 [V22 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V23 tmp12 [V23 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V24 tmp13 [V24 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V25 tmp14 [V25 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V26 tmp15 [V26 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V27 tmp16 [V27 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V28 tmp17 [V28 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V29 tmp18 [V29 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V30 tmp19 [V30 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V31 tmp20 [V31 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V32 tmp21 [V32 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V33 tmp22 [V33 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V34 tmp23 [V34 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V35 tmp24 [V35 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V36 tmp25 [V36 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V37 tmp26 [V37 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V38 tmp27 [V38 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V39 tmp28 [V39 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V40 tmp29 [V40 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V41 tmp30 [V41 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V42 tmp31 [V42 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V43 tmp32 [V43 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V44 tmp33 [V44 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V45 tmp34 [V45 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V46 tmp35 [V46 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V47 tmp36 [V47 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V48 tmp37 [V48 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V49 tmp38 [V49 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V50 tmp39 [V50 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V51 tmp40 [V51 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V52 tmp41 [V52 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V53 tmp42 [V53 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V54 tmp43 [V54 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V55 tmp44 [V55 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V56 tmp45 [V56 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V57 tmp46 [V57 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V58 tmp47 [V58 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V59 tmp48 [V59 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V60 tmp49 [V60 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V61 tmp50 [V61 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V62 tmp51 [V62 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V63 tmp52 [V63 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V64 tmp53 [V64 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V65 tmp54 [V65 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" -; V66 tmp55 [V66,T08] ( 4, 16 ) long -> rbx "Inline stloc first use temp" -; V67 tmp56 [V67,T38] ( 2, 8 ) long -> rax "Inline stloc first use temp" +; V66 tmp55 [V66,T08] ( 4, 16 ) long -> r15 "Inline stloc first use temp" +; V67 tmp56 [V67,T38] ( 2, 8 ) long -> rdx "Inline stloc first use temp" ;* V68 tmp57 [V68 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V69 tmp58 [V69 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V70 tmp59 [V70 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" -; V71 tmp60 [V71,T22] ( 3, 12 ) long -> rdx "Inline stloc first use temp" +; V71 tmp60 [V71,T22] ( 3, 12 ) long -> r10 "Inline stloc first use temp" ; V72 tmp61 [V72,T39] ( 2, 8 ) long -> rbx "Inline stloc first use temp" ;* V73 tmp62 [V73 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V74 tmp63 [V74 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V75 tmp64 [V75 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V76 tmp65 [V76 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V77 tmp66 [V77 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V78 tmp67 [V78 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V79 tmp68 [V79 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V80 tmp69 [V80 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V81 tmp70 [V81 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V82 tmp71 [V82 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V83 tmp72 [V83 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V84 tmp73 [V84 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V85 tmp74 [V85 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V86 tmp75 [V86 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V87 tmp76 [V87 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V88 tmp77 [V88 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" -; V89 tmp78 [V89,T09] ( 4, 16 ) long -> r11 "Inline stloc first use temp" -; V90 tmp79 [V90,T40] ( 2, 8 ) long -> rax "Inline stloc first use temp" +; V89 tmp78 [V89,T09] ( 4, 16 ) long -> r10 "Inline stloc first use temp" +; V90 tmp79 [V90,T40] ( 2, 8 ) long -> rdx "Inline stloc first use temp" ;* V91 tmp80 [V91 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V92 tmp81 [V92 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V93 tmp82 [V93 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V94 tmp83 [V94 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V95 tmp84 [V95 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V96 tmp85 [V96 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V97 tmp86 [V97 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V98 tmp87 [V98 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V99 tmp88 [V99 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V100 tmp89 [V100 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V101 tmp90 [V101 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V102 tmp91 [V102 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V103 tmp92 [V103,T23] ( 3, 12 ) long -> rbx "Inline stloc first use temp" -; V104 tmp93 [V104,T41] ( 2, 8 ) long -> r11 "Inline stloc first use temp" +; V104 tmp93 [V104,T41] ( 2, 8 ) long -> r10 "Inline stloc first use temp" ;* V105 tmp94 [V105 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V106 tmp95 [V106 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V107 tmp96 [V107 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V108 tmp97 [V108 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V109 tmp98 [V109 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V110 tmp99 [V110 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V111 tmp100 [V111 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V112 tmp101 [V112 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V113 tmp102 [V113 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V114 tmp103 [V114 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V115 tmp104 [V115 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V116 tmp105 [V116 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V117 tmp106 [V117 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V118 tmp107 [V118 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V119 tmp108 [V119 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V120 tmp109 [V120 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" -; V121 tmp110 [V121,T10] ( 4, 16 ) long -> rbx "Inline stloc first use temp" -; V122 tmp111 [V122,T42] ( 2, 8 ) long -> rax "Inline stloc first use temp" +; V121 tmp110 [V121,T10] ( 4, 16 ) long -> r11 "Inline stloc first use temp" +; V122 tmp111 [V122,T42] ( 2, 8 ) long -> rdx "Inline stloc first use temp" ;* V123 tmp112 [V123 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V124 tmp113 [V124 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V125 tmp114 [V125 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V126 tmp115 [V126 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V127 tmp116 [V127 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V128 tmp117 [V128 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V129 tmp118 [V129 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V130 tmp119 [V130 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V131 tmp120 [V131 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V132 tmp121 [V132 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V133 tmp122 [V133 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V134 tmp123 [V134 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" -; V135 tmp124 [V135,T24] ( 3, 12 ) long -> r11 "Inline stloc first use temp" -; V136 tmp125 [V136,T43] ( 2, 8 ) long -> rdx "Inline stloc first use temp" +; V135 tmp124 [V135,T24] ( 3, 12 ) long -> r10 "Inline stloc first use temp" +; V136 tmp125 [V136,T43] ( 2, 8 ) long -> r11 "Inline stloc first use temp" ;* V137 tmp126 [V137 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V138 tmp127 [V138 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V139 tmp128 [V139 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V140 tmp129 [V140 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V141 tmp130 [V141 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V142 tmp131 [V142 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V143 tmp132 [V143 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V144 tmp133 [V144 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V145 tmp134 [V145 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V146 tmp135 [V146 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V147 tmp136 [V147 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V148 tmp137 [V148 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V149 tmp138 [V149 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V150 tmp139 [V150 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V151 tmp140 [V151 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V152 tmp141 [V152 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" -; V153 tmp142 [V153,T11] ( 4, 16 ) long -> r11 "Inline stloc first use temp" -; V154 tmp143 [V154,T44] ( 2, 8 ) long -> rax "Inline stloc first use temp" +; V153 tmp142 [V153,T11] ( 4, 16 ) long -> r10 "Inline stloc first use temp" +; V154 tmp143 [V154,T44] ( 2, 8 ) long -> rdx "Inline stloc first use temp" ;* V155 tmp144 [V155 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V156 tmp145 [V156 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V157 tmp146 [V157 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V158 tmp147 [V158 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V159 tmp148 [V159 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V160 tmp149 [V160 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V161 tmp150 [V161 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V162 tmp151 [V162 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V163 tmp152 [V163 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V164 tmp153 [V164 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V165 tmp154 [V165 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V166 tmp155 [V166 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" -; V167 tmp156 [V167,T25] ( 3, 12 ) long -> rax "Inline stloc first use temp" -; V168 tmp157 [V168,T45] ( 2, 8 ) long -> r11 "Inline stloc first use temp" +; V167 tmp156 [V167,T25] ( 3, 12 ) long -> r11 "Inline stloc first use temp" +; V168 tmp157 [V168,T45] ( 2, 8 ) long -> r10 "Inline stloc first use temp" ;* V169 tmp158 [V169 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V170 tmp159 [V170 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V171 tmp160 [V171 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V172 tmp161 [V172 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V173 tmp162 [V173 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V174 tmp163 [V174 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V175 tmp164 [V175 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V176 tmp165 [V176 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V177 tmp166 [V177 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V178 tmp167 [V178 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V179 tmp168 [V179 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V180 tmp169 [V180 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V181 tmp170 [V181 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V182 tmp171 [V182 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V183 tmp172 [V183 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V184 tmp173 [V184 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V185 tmp174 [V185 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V186 tmp175 [V186 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V187 tmp176 [V187 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V188 tmp177 [V188 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V189 tmp178 [V189 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V190 tmp179 [V190 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V191 tmp180 [V191 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" -; V192 tmp181 [V192,T07] ( 8, 16 ) long -> rbx "Inline stloc first use temp" +; V192 tmp181 [V192,T07] ( 8, 16 ) long -> registers "Inline stloc first use temp" ; V193 tmp182 [V193,T31] ( 4, 8 ) long -> registers "Inline stloc first use temp" ;* V194 tmp183 [V194 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V195 tmp184 [V195 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V196 tmp185 [V196 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" -; V197 tmp186 [V197,T20] ( 6, 12 ) long -> r15 "Inline stloc first use temp" -; V198 tmp187 [V198,T32] ( 4, 8 ) long -> registers "Inline stloc first use temp" +; V197 tmp186 [V197,T20] ( 6, 12 ) long -> r14 "Inline stloc first use temp" +; V198 tmp187 [V198,T32] ( 4, 8 ) long -> r10 "Inline stloc first use temp" ;* V199 tmp188 [V199 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V200 tmp189 [V200 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V201 tmp190 [V201 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V202 tmp191 [V202 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V203 tmp192 [V203 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V204 tmp193 [V204 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V205 tmp194 [V205 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V206 tmp195 [V206 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V207 tmp196 [V207 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V208 tmp197 [V208,T01] ( 13, 41 ) byref -> rdi single-def "field V00._reference (fldOffset=0x0)" P-INDEP ; V209 tmp198 [V209,T05] ( 7, 17.29) int -> rsi single-def "field V00._length (fldOffset=0x8)" P-INDEP -; V210 tmp199 [V210,T03] ( 7, 21 ) byref -> [rbp-0x28] single-def "field V01._reference (fldOffset=0x0)" P-INDEP +; V210 tmp199 [V210,T03] ( 7, 21 ) byref -> [rbp-0x20] single-def "field V01._reference (fldOffset=0x0)" P-INDEP ; V211 tmp200 [V211,T30] ( 7, 7.79) int -> rcx single-def "field V01._length (fldOffset=0x8)" P-INDEP ;* V212 tmp201 [V212 ] ( 0, 0 ) long -> zero-ref "field V06._lower (fldOffset=0x0)" P-INDEP ;* V213 tmp202 [V213 ] ( 0, 0 ) long -> zero-ref "field V06._upper (fldOffset=0x8)" P-INDEP ;* V214 tmp203 [V214 ] ( 0, 0 ) long -> zero-ref "field V07._lower (fldOffset=0x0)" P-INDEP ;* V215 tmp204 [V215 ] ( 0, 0 ) long -> zero-ref "field V07._upper (fldOffset=0x8)" P-INDEP ;* V216 tmp205 [V216 ] ( 0, 0 ) long -> zero-ref "field V08._lower (fldOffset=0x0)" P-INDEP ;* V217 tmp206 [V217 ] ( 0, 0 ) long -> zero-ref "field V08._upper (fldOffset=0x8)" P-INDEP ;* V218 tmp207 [V218 ] ( 0, 0 ) long -> zero-ref "field V09._lower (fldOffset=0x0)" P-INDEP ;* V219 tmp208 [V219 ] ( 0, 0 ) long -> zero-ref "field V09._upper (fldOffset=0x8)" P-INDEP ;* V220 tmp209 [V220 ] ( 0, 0 ) long -> zero-ref "field V10._lower (fldOffset=0x0)" P-INDEP ;* V221 tmp210 [V221 ] ( 0, 0 ) long -> zero-ref "field V10._upper (fldOffset=0x8)" P-INDEP ;* V222 tmp211 [V222 ] ( 0, 0 ) long -> zero-ref "field V12._lower (fldOffset=0x0)" P-INDEP ;* V223 tmp212 [V223 ] ( 0, 0 ) long -> zero-ref "field V12._upper (fldOffset=0x8)" P-INDEP ;* V224 tmp213 [V224 ] ( 0, 0 ) long -> zero-ref "field V13._lower (fldOffset=0x0)" P-INDEP ;* V225 tmp214 [V225 ] ( 0, 0 ) long -> zero-ref "field V13._upper (fldOffset=0x8)" P-INDEP ;* V226 tmp215 [V226 ] ( 0, 0 ) long -> zero-ref "field V14._lower (fldOffset=0x0)" P-INDEP ;* V227 tmp216 [V227 ] ( 0, 0 ) long -> zero-ref "field V14._upper (fldOffset=0x8)" P-INDEP ;* V228 tmp217 [V228 ] ( 0, 0 ) long -> zero-ref "field V15._lower (fldOffset=0x0)" P-INDEP ;* V229 tmp218 [V229 ] ( 0, 0 ) long -> zero-ref "field V15._upper (fldOffset=0x8)" P-INDEP ;* V230 tmp219 [V230 ] ( 0, 0 ) long -> zero-ref "field V16._lower (fldOffset=0x0)" P-INDEP ;* V231 tmp220 [V231 ] ( 0, 0 ) long -> zero-ref "field V16._upper (fldOffset=0x8)" P-INDEP ;* V232 tmp221 [V232 ] ( 0, 0 ) long -> zero-ref "field V17._lower (fldOffset=0x0)" P-INDEP ;* V233 tmp222 [V233 ] ( 0, 0 ) long -> zero-ref "field V17._upper (fldOffset=0x8)" P-INDEP ;* V234 tmp223 [V234 ] ( 0, 0 ) long -> zero-ref "field V19._lower (fldOffset=0x0)" P-INDEP ;* V235 tmp224 [V235 ] ( 0, 0 ) long -> zero-ref "field V19._upper (fldOffset=0x8)" P-INDEP ;* V236 tmp225 [V236 ] ( 0, 0 ) long -> zero-ref "field V20._lower (fldOffset=0x0)" P-INDEP ;* V237 tmp226 [V237 ] ( 0, 0 ) long -> zero-ref "field V20._upper (fldOffset=0x8)" P-INDEP ;* V238 tmp227 [V238 ] ( 0, 0 ) long -> zero-ref "field V21._lower (fldOffset=0x0)" P-INDEP ;* V239 tmp228 [V239 ] ( 0, 0 ) long -> zero-ref "field V21._upper (fldOffset=0x8)" P-INDEP ;* V240 tmp229 [V240 ] ( 0, 0 ) long -> zero-ref "field V22._lower (fldOffset=0x0)" P-INDEP ;* V241 tmp230 [V241 ] ( 0, 0 ) long -> zero-ref "field V22._upper (fldOffset=0x8)" P-INDEP ;* V242 tmp231 [V242 ] ( 0, 0 ) long -> zero-ref "field V23._lower (fldOffset=0x0)" P-INDEP ;* V243 tmp232 [V243 ] ( 0, 0 ) long -> zero-ref "field V23._upper (fldOffset=0x8)" P-INDEP ;* V244 tmp233 [V244 ] ( 0, 0 ) long -> zero-ref "field V24._lower (fldOffset=0x0)" P-INDEP ;* V245 tmp234 [V245 ] ( 0, 0 ) long -> zero-ref "field V24._upper (fldOffset=0x8)" P-INDEP ;* V246 tmp235 [V246 ] ( 0, 0 ) long -> zero-ref "field V25._lower (fldOffset=0x0)" P-INDEP ;* V247 tmp236 [V247 ] ( 0, 0 ) long -> zero-ref "field V25._upper (fldOffset=0x8)" P-INDEP ;* V248 tmp237 [V248 ] ( 0, 0 ) long -> zero-ref "field V27._lower (fldOffset=0x0)" P-INDEP ;* V249 tmp238 [V249 ] ( 0, 0 ) long -> zero-ref "field V27._upper (fldOffset=0x8)" P-INDEP ;* V250 tmp239 [V250 ] ( 0, 0 ) long -> zero-ref "field V28._lower (fldOffset=0x0)" P-INDEP ;* V251 tmp240 [V251 ] ( 0, 0 ) long -> zero-ref "field V28._upper (fldOffset=0x8)" P-INDEP ;* V252 tmp241 [V252 ] ( 0, 0 ) long -> zero-ref "field V29._lower (fldOffset=0x0)" P-INDEP ;* V253 tmp242 [V253 ] ( 0, 0 ) long -> zero-ref "field V29._upper (fldOffset=0x8)" P-INDEP ;* V254 tmp243 [V254 ] ( 0, 0 ) long -> zero-ref "field V30._lower (fldOffset=0x0)" P-INDEP ;* V255 tmp244 [V255 ] ( 0, 0 ) long -> zero-ref "field V30._upper (fldOffset=0x8)" P-INDEP ;* V256 tmp245 [V256 ] ( 0, 0 ) long -> zero-ref "field V31._lower (fldOffset=0x0)" P-INDEP ;* V257 tmp246 [V257 ] ( 0, 0 ) long -> zero-ref "field V31._upper (fldOffset=0x8)" P-INDEP ;* V258 tmp247 [V258 ] ( 0, 0 ) long -> zero-ref "field V32._lower (fldOffset=0x0)" P-INDEP ;* V259 tmp248 [V259 ] ( 0, 0 ) long -> zero-ref "field V32._upper (fldOffset=0x8)" P-INDEP ;* V260 tmp249 [V260 ] ( 0, 0 ) long -> zero-ref "field V33._lower (fldOffset=0x0)" P-INDEP ;* V261 tmp250 [V261 ] ( 0, 0 ) long -> zero-ref "field V33._upper (fldOffset=0x8)" P-INDEP ;* V262 tmp251 [V262 ] ( 0, 0 ) long -> zero-ref "field V35._lower (fldOffset=0x0)" P-INDEP ;* V263 tmp252 [V263 ] ( 0, 0 ) long -> zero-ref "field V35._upper (fldOffset=0x8)" P-INDEP ;* V264 tmp253 [V264 ] ( 0, 0 ) long -> zero-ref "field V36._lower (fldOffset=0x0)" P-INDEP ;* V265 tmp254 [V265 ] ( 0, 0 ) long -> zero-ref "field V36._upper (fldOffset=0x8)" P-INDEP ;* V266 tmp255 [V266 ] ( 0, 0 ) long -> zero-ref "field V37._lower (fldOffset=0x0)" P-INDEP ;* V267 tmp256 [V267 ] ( 0, 0 ) long -> zero-ref "field V37._upper (fldOffset=0x8)" P-INDEP ;* V268 tmp257 [V268 ] ( 0, 0 ) long -> zero-ref "field V38._lower (fldOffset=0x0)" P-INDEP ;* V269 tmp258 [V269 ] ( 0, 0 ) long -> zero-ref "field V38._upper (fldOffset=0x8)" P-INDEP ;* V270 tmp259 [V270 ] ( 0, 0 ) long -> zero-ref "field V39._lower (fldOffset=0x0)" P-INDEP ;* V271 tmp260 [V271 ] ( 0, 0 ) long -> zero-ref "field V39._upper (fldOffset=0x8)" P-INDEP ;* V272 tmp261 [V272 ] ( 0, 0 ) long -> zero-ref "field V40._lower (fldOffset=0x0)" P-INDEP ;* V273 tmp262 [V273 ] ( 0, 0 ) long -> zero-ref "field V40._upper (fldOffset=0x8)" P-INDEP ;* V274 tmp263 [V274 ] ( 0, 0 ) long -> zero-ref "field V41._lower (fldOffset=0x0)" P-INDEP ;* V275 tmp264 [V275 ] ( 0, 0 ) long -> zero-ref "field V41._upper (fldOffset=0x8)" P-INDEP ;* V276 tmp265 [V276 ] ( 0, 0 ) long -> zero-ref "field V43._lower (fldOffset=0x0)" P-INDEP ;* V277 tmp266 [V277 ] ( 0, 0 ) long -> zero-ref "field V43._upper (fldOffset=0x8)" P-INDEP ;* V278 tmp267 [V278 ] ( 0, 0 ) long -> zero-ref "field V44._lower (fldOffset=0x0)" P-INDEP ;* V279 tmp268 [V279 ] ( 0, 0 ) long -> zero-ref "field V44._upper (fldOffset=0x8)" P-INDEP ;* V280 tmp269 [V280 ] ( 0, 0 ) long -> zero-ref "field V45._lower (fldOffset=0x0)" P-INDEP ;* V281 tmp270 [V281 ] ( 0, 0 ) long -> zero-ref "field V45._upper (fldOffset=0x8)" P-INDEP ;* V282 tmp271 [V282 ] ( 0, 0 ) long -> zero-ref "field V46._lower (fldOffset=0x0)" P-INDEP ;* V283 tmp272 [V283 ] ( 0, 0 ) long -> zero-ref "field V46._upper (fldOffset=0x8)" P-INDEP ;* V284 tmp273 [V284 ] ( 0, 0 ) long -> zero-ref "field V47._lower (fldOffset=0x0)" P-INDEP ;* V285 tmp274 [V285 ] ( 0, 0 ) long -> zero-ref "field V47._upper (fldOffset=0x8)" P-INDEP ;* V286 tmp275 [V286 ] ( 0, 0 ) long -> zero-ref "field V48._lower (fldOffset=0x0)" P-INDEP ;* V287 tmp276 [V287 ] ( 0, 0 ) long -> zero-ref "field V48._upper (fldOffset=0x8)" P-INDEP ;* V288 tmp277 [V288 ] ( 0, 0 ) long -> zero-ref "field V49._lower (fldOffset=0x0)" P-INDEP ;* V289 tmp278 [V289 ] ( 0, 0 ) long -> zero-ref "field V49._upper (fldOffset=0x8)" P-INDEP ;* V290 tmp279 [V290 ] ( 0, 0 ) long -> zero-ref "field V51._lower (fldOffset=0x0)" P-INDEP ;* V291 tmp280 [V291 ] ( 0, 0 ) long -> zero-ref "field V51._upper (fldOffset=0x8)" P-INDEP ; V292 tmp281 [V292,T46] ( 2, 8 ) long -> rbx "field V53._lower (fldOffset=0x0)" P-INDEP ;* V293 tmp282 [V293 ] ( 0, 0 ) long -> zero-ref "field V53._upper (fldOffset=0x8)" P-INDEP ;* V294 tmp283 [V294 ] ( 0, 0 ) long -> zero-ref "field V54._lower (fldOffset=0x0)" P-INDEP ;* V295 tmp284 [V295 ] ( 0, 0 ) long -> zero-ref "field V54._upper (fldOffset=0x8)" P-INDEP ;* V296 tmp285 [V296 ] ( 0, 0 ) long -> zero-ref "field V56._lower (fldOffset=0x0)" P-INDEP ;* V297 tmp286 [V297 ] ( 0, 0 ) long -> zero-ref "field V56._upper (fldOffset=0x8)" P-INDEP ;* V298 tmp287 [V298 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V60.Item1 (fldOffset=0x0)" P-DEP ;* V299 tmp288 [V299 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V60.Item2 (fldOffset=0x8)" P-DEP -; V300 tmp289 [V300,T26] ( 3, 12 ) long -> rax "field V61.Item1 (fldOffset=0x0)" P-INDEP -; V301 tmp290 [V301,T47] ( 2, 8 ) long -> rdx "field V61.Item2 (fldOffset=0x8)" P-INDEP -; V302 tmp291 [V302,T48] ( 2, 8 ) long -> rbx "field V65._lower (fldOffset=0x0)" P-INDEP +; V300 tmp289 [V300,T26] ( 3, 12 ) long -> rdx "field V61.Item1 (fldOffset=0x0)" P-INDEP +; V301 tmp290 [V301,T47] ( 2, 8 ) long -> rbx "field V61.Item2 (fldOffset=0x8)" P-INDEP +; V302 tmp291 [V302,T48] ( 2, 8 ) long -> r15 "field V65._lower (fldOffset=0x0)" P-INDEP ;* V303 tmp292 [V303 ] ( 0, 0 ) long -> zero-ref "field V65._upper (fldOffset=0x8)" P-INDEP ;* V304 tmp293 [V304 ] ( 0, 0 ) long -> zero-ref "field V68._lower (fldOffset=0x0)" P-INDEP -; V305 tmp294 [V305,T49] ( 2, 8 ) long -> rax "field V68._upper (fldOffset=0x8)" P-INDEP +; V305 tmp294 [V305,T49] ( 2, 8 ) long -> rdx "field V68._upper (fldOffset=0x8)" P-INDEP ;* V306 tmp295 [V306 ] ( 0, 0 ) long -> zero-ref "field V70._lower (fldOffset=0x0)" P-INDEP ;* V307 tmp296 [V307 ] ( 0, 0 ) long -> zero-ref "field V70._upper (fldOffset=0x8)" P-INDEP ;* V308 tmp297 [V308 ] ( 0, 0 ) long -> zero-ref "field V73._lower (fldOffset=0x0)" P-INDEP ; V309 tmp298 [V309,T50] ( 2, 8 ) long -> rbx "field V73._upper (fldOffset=0x8)" P-INDEP -; V310 tmp299 [V310,T51] ( 2, 8 ) long -> rax "field V76._lower (fldOffset=0x0)" P-INDEP +; V310 tmp299 [V310,T51] ( 2, 8 ) long -> r15 "field V76._lower (fldOffset=0x0)" P-INDEP ;* V311 tmp300 [V311 ] ( 0, 0 ) long -> zero-ref "field V76._upper (fldOffset=0x8)" P-INDEP ;* V312 tmp301 [V312 ] ( 0, 0 ) long -> zero-ref "field V77._lower (fldOffset=0x0)" P-INDEP ;* V313 tmp302 [V313 ] ( 0, 0 ) long -> zero-ref "field V77._upper (fldOffset=0x8)" P-INDEP ;* V314 tmp303 [V314 ] ( 0, 0 ) long -> zero-ref "field V79._lower (fldOffset=0x0)" P-INDEP ;* V315 tmp304 [V315 ] ( 0, 0 ) long -> zero-ref "field V79._upper (fldOffset=0x8)" P-INDEP ;* V316 tmp305 [V316 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V83.Item1 (fldOffset=0x0)" P-DEP ;* V317 tmp306 [V317 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V83.Item2 (fldOffset=0x8)" P-DEP -; V318 tmp307 [V318,T27] ( 3, 12 ) long -> rax "field V84.Item1 (fldOffset=0x0)" P-INDEP -; V319 tmp308 [V319,T52] ( 2, 8 ) long -> rdx "field V84.Item2 (fldOffset=0x8)" P-INDEP -; V320 tmp309 [V320,T53] ( 2, 8 ) long -> r11 "field V88._lower (fldOffset=0x0)" P-INDEP +; V318 tmp307 [V318,T27] ( 3, 12 ) long -> rdx "field V84.Item1 (fldOffset=0x0)" P-INDEP +; V319 tmp308 [V319,T52] ( 2, 8 ) long -> r15 "field V84.Item2 (fldOffset=0x8)" P-INDEP +; V320 tmp309 [V320,T53] ( 2, 8 ) long -> r10 "field V88._lower (fldOffset=0x0)" P-INDEP ;* V321 tmp310 [V321 ] ( 0, 0 ) long -> zero-ref "field V88._upper (fldOffset=0x8)" P-INDEP ;* V322 tmp311 [V322 ] ( 0, 0 ) long -> zero-ref "field V91._lower (fldOffset=0x0)" P-INDEP -; V323 tmp312 [V323,T54] ( 2, 8 ) long -> rax "field V91._upper (fldOffset=0x8)" P-INDEP +; V323 tmp312 [V323,T54] ( 2, 8 ) long -> rdx "field V91._upper (fldOffset=0x8)" P-INDEP ;* V324 tmp313 [V324 ] ( 0, 0 ) long -> zero-ref "field V93._lower (fldOffset=0x0)" P-INDEP ;* V325 tmp314 [V325 ] ( 0, 0 ) long -> zero-ref "field V93._upper (fldOffset=0x8)" P-INDEP ;* V326 tmp315 [V326 ] ( 0, 0 ) long -> zero-ref "field V96._lower (fldOffset=0x0)" P-INDEP ;* V327 tmp316 [V327 ] ( 0, 0 ) long -> zero-ref "field V96._upper (fldOffset=0x8)" P-INDEP ;* V328 tmp317 [V328 ] ( 0, 0 ) long -> zero-ref "field V98._lower (fldOffset=0x0)" P-INDEP ;* V329 tmp318 [V329 ] ( 0, 0 ) long -> zero-ref "field V98._upper (fldOffset=0x8)" P-INDEP ;* V330 tmp319 [V330 ] ( 0, 0 ) long -> zero-ref "field V101._lower (fldOffset=0x0)" P-INDEP ;* V331 tmp320 [V331 ] ( 0, 0 ) long -> zero-ref "field V101._upper (fldOffset=0x8)" P-INDEP ;* V332 tmp321 [V332 ] ( 0, 0 ) long -> zero-ref "field V105._lower (fldOffset=0x0)" P-INDEP -; V333 tmp322 [V333,T55] ( 2, 8 ) long -> r11 "field V105._upper (fldOffset=0x8)" P-INDEP -; V334 tmp323 [V334,T56] ( 2, 8 ) long -> rax "field V108._lower (fldOffset=0x0)" P-INDEP +; V333 tmp322 [V333,T55] ( 2, 8 ) long -> r10 "field V105._upper (fldOffset=0x8)" P-INDEP +; V334 tmp323 [V334,T56] ( 2, 8 ) long -> r15 "field V108._lower (fldOffset=0x0)" P-INDEP ;* V335 tmp324 [V335 ] ( 0, 0 ) long -> zero-ref "field V108._upper (fldOffset=0x8)" P-INDEP ;* V336 tmp325 [V336 ] ( 0, 0 ) long -> zero-ref "field V109._lower (fldOffset=0x0)" P-INDEP ;* V337 tmp326 [V337 ] ( 0, 0 ) long -> zero-ref "field V109._upper (fldOffset=0x8)" P-INDEP ;* V338 tmp327 [V338 ] ( 0, 0 ) long -> zero-ref "field V111._lower (fldOffset=0x0)" P-INDEP ;* V339 tmp328 [V339 ] ( 0, 0 ) long -> zero-ref "field V111._upper (fldOffset=0x8)" P-INDEP ;* V340 tmp329 [V340 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V115.Item1 (fldOffset=0x0)" P-DEP ;* V341 tmp330 [V341 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V115.Item2 (fldOffset=0x8)" P-DEP -; V342 tmp331 [V342,T28] ( 3, 12 ) long -> rax "field V116.Item1 (fldOffset=0x0)" P-INDEP -; V343 tmp332 [V343,T57] ( 2, 8 ) long -> rdx "field V116.Item2 (fldOffset=0x8)" P-INDEP -; V344 tmp333 [V344,T58] ( 2, 8 ) long -> rbx "field V120._lower (fldOffset=0x0)" P-INDEP +; V342 tmp331 [V342,T28] ( 3, 12 ) long -> rdx "field V116.Item1 (fldOffset=0x0)" P-INDEP +; V343 tmp332 [V343,T57] ( 2, 8 ) long -> r15 "field V116.Item2 (fldOffset=0x8)" P-INDEP +; V344 tmp333 [V344,T58] ( 2, 8 ) long -> r11 "field V120._lower (fldOffset=0x0)" P-INDEP ;* V345 tmp334 [V345 ] ( 0, 0 ) long -> zero-ref "field V120._upper (fldOffset=0x8)" P-INDEP ;* V346 tmp335 [V346 ] ( 0, 0 ) long -> zero-ref "field V123._lower (fldOffset=0x0)" P-INDEP -; V347 tmp336 [V347,T59] ( 2, 8 ) long -> rax "field V123._upper (fldOffset=0x8)" P-INDEP +; V347 tmp336 [V347,T59] ( 2, 8 ) long -> rdx "field V123._upper (fldOffset=0x8)" P-INDEP ;* V348 tmp337 [V348 ] ( 0, 0 ) long -> zero-ref "field V125._lower (fldOffset=0x0)" P-INDEP ;* V349 tmp338 [V349 ] ( 0, 0 ) long -> zero-ref "field V125._upper (fldOffset=0x8)" P-INDEP ;* V350 tmp339 [V350 ] ( 0, 0 ) long -> zero-ref "field V128._lower (fldOffset=0x0)" P-INDEP ;* V351 tmp340 [V351 ] ( 0, 0 ) long -> zero-ref "field V128._upper (fldOffset=0x8)" P-INDEP ;* V352 tmp341 [V352 ] ( 0, 0 ) long -> zero-ref "field V130._lower (fldOffset=0x0)" P-INDEP ;* V353 tmp342 [V353 ] ( 0, 0 ) long -> zero-ref "field V130._upper (fldOffset=0x8)" P-INDEP ;* V354 tmp343 [V354 ] ( 0, 0 ) long -> zero-ref "field V133._lower (fldOffset=0x0)" P-INDEP ;* V355 tmp344 [V355 ] ( 0, 0 ) long -> zero-ref "field V133._upper (fldOffset=0x8)" P-INDEP ;* V356 tmp345 [V356 ] ( 0, 0 ) long -> zero-ref "field V137._lower (fldOffset=0x0)" P-INDEP -; V357 tmp346 [V357,T60] ( 2, 8 ) long -> [rbp-0x20] spill-single-def "field V137._upper (fldOffset=0x8)" P-INDEP +; V357 tmp346 [V357,T60] ( 2, 8 ) long -> r11 "field V137._upper (fldOffset=0x8)" P-INDEP ; V358 tmp347 [V358,T61] ( 2, 8 ) long -> r15 "field V140._lower (fldOffset=0x0)" P-INDEP ;* V359 tmp348 [V359 ] ( 0, 0 ) long -> zero-ref "field V140._upper (fldOffset=0x8)" P-INDEP ;* V360 tmp349 [V360 ] ( 0, 0 ) long -> zero-ref "field V141._lower (fldOffset=0x0)" P-INDEP ;* V361 tmp350 [V361 ] ( 0, 0 ) long -> zero-ref "field V141._upper (fldOffset=0x8)" P-INDEP ;* V362 tmp351 [V362 ] ( 0, 0 ) long -> zero-ref "field V143._lower (fldOffset=0x0)" P-INDEP ;* V363 tmp352 [V363 ] ( 0, 0 ) long -> zero-ref "field V143._upper (fldOffset=0x8)" P-INDEP ;* V364 tmp353 [V364 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V147.Item1 (fldOffset=0x0)" P-DEP ;* V365 tmp354 [V365 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V147.Item2 (fldOffset=0x8)" P-DEP -; V366 tmp355 [V366,T29] ( 3, 12 ) long -> rax "field V148.Item1 (fldOffset=0x0)" P-INDEP -; V367 tmp356 [V367,T62] ( 2, 8 ) long -> rdx "field V148.Item2 (fldOffset=0x8)" P-INDEP -; V368 tmp357 [V368,T63] ( 2, 8 ) long -> r11 "field V152._lower (fldOffset=0x0)" P-INDEP +; V366 tmp355 [V366,T29] ( 3, 12 ) long -> rdx "field V148.Item1 (fldOffset=0x0)" P-INDEP +; V367 tmp356 [V367,T62] ( 2, 8 ) long -> r15 "field V148.Item2 (fldOffset=0x8)" P-INDEP +; V368 tmp357 [V368,T63] ( 2, 8 ) long -> r10 "field V152._lower (fldOffset=0x0)" P-INDEP ;* V369 tmp358 [V369 ] ( 0, 0 ) long -> zero-ref "field V152._upper (fldOffset=0x8)" P-INDEP ;* V370 tmp359 [V370 ] ( 0, 0 ) long -> zero-ref "field V155._lower (fldOffset=0x0)" P-INDEP ; V371 tmp360 [V371,T64] ( 2, 8 ) long -> rdx "field V155._upper (fldOffset=0x8)" P-INDEP ;* V372 tmp361 [V372 ] ( 0, 0 ) long -> zero-ref "field V157._lower (fldOffset=0x0)" P-INDEP ;* V373 tmp362 [V373 ] ( 0, 0 ) long -> zero-ref "field V157._upper (fldOffset=0x8)" P-INDEP ;* V374 tmp363 [V374 ] ( 0, 0 ) long -> zero-ref "field V160._lower (fldOffset=0x0)" P-INDEP ;* V375 tmp364 [V375 ] ( 0, 0 ) long -> zero-ref "field V160._upper (fldOffset=0x8)" P-INDEP ;* V376 tmp365 [V376 ] ( 0, 0 ) long -> zero-ref "field V162._lower (fldOffset=0x0)" P-INDEP ;* V377 tmp366 [V377 ] ( 0, 0 ) long -> zero-ref "field V162._upper (fldOffset=0x8)" P-INDEP ;* V378 tmp367 [V378 ] ( 0, 0 ) long -> zero-ref "field V165._lower (fldOffset=0x0)" P-INDEP ;* V379 tmp368 [V379 ] ( 0, 0 ) long -> zero-ref "field V165._upper (fldOffset=0x8)" P-INDEP ;* V380 tmp369 [V380 ] ( 0, 0 ) long -> zero-ref "field V169._lower (fldOffset=0x0)" P-INDEP -; V381 tmp370 [V381,T65] ( 2, 8 ) long -> rdx "field V169._upper (fldOffset=0x8)" P-INDEP +; V381 tmp370 [V381,T65] ( 2, 8 ) long -> r10 "field V169._upper (fldOffset=0x8)" P-INDEP ;* V382 tmp371 [V382 ] ( 0, 0 ) long -> zero-ref "field V171._lower (fldOffset=0x0)" P-INDEP ;* V383 tmp372 [V383 ] ( 0, 0 ) long -> zero-ref "field V171._upper (fldOffset=0x8)" P-INDEP ;* V384 tmp373 [V384 ] ( 0, 0 ) long -> zero-ref "field V174._lower (fldOffset=0x0)" P-INDEP ;* V385 tmp374 [V385 ] ( 0, 0 ) long -> zero-ref "field V174._upper (fldOffset=0x8)" P-INDEP ;* V386 tmp375 [V386 ] ( 0, 0 ) long -> zero-ref "field V176._lower (fldOffset=0x0)" P-INDEP ;* V387 tmp376 [V387 ] ( 0, 0 ) long -> zero-ref "field V176._upper (fldOffset=0x8)" P-INDEP ; V388 tmp377 [V388,T33] ( 4, 8 ) long -> registers "field V179._lower (fldOffset=0x0)" P-INDEP ;* V389 tmp378 [V389 ] ( 0, 0 ) long -> zero-ref "field V179._upper (fldOffset=0x8)" P-INDEP ;* V390 tmp379 [V390 ] ( 0, 0 ) long -> zero-ref "field V180._lower (fldOffset=0x0)" P-INDEP ;* V391 tmp380 [V391 ] ( 0, 0 ) long -> zero-ref "field V180._upper (fldOffset=0x8)" P-INDEP ;* V392 tmp381 [V392 ] ( 0, 0 ) long -> zero-ref "field V182._lower (fldOffset=0x0)" P-INDEP ;* V393 tmp382 [V393 ] ( 0, 0 ) long -> zero-ref "field V182._upper (fldOffset=0x8)" P-INDEP ;* V394 tmp383 [V394 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V186.Item1 (fldOffset=0x0)" P-DEP ;* V395 tmp384 [V395 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V186.Item2 (fldOffset=0x8)" P-DEP -; V396 tmp385 [V396,T21] ( 6, 12 ) long -> rax "field V187.Item1 (fldOffset=0x0)" P-INDEP -; V397 tmp386 [V397,T34] ( 4, 8 ) long -> rdx "field V187.Item2 (fldOffset=0x8)" P-INDEP -; V398 tmp387 [V398,T35] ( 4, 8 ) long -> rbx "field V191._lower (fldOffset=0x0)" P-INDEP +; V396 tmp385 [V396,T21] ( 6, 12 ) long -> registers "field V187.Item1 (fldOffset=0x0)" P-INDEP +; V397 tmp386 [V397,T34] ( 4, 8 ) long -> registers "field V187.Item2 (fldOffset=0x8)" P-INDEP +; V398 tmp387 [V398,T35] ( 4, 8 ) long -> registers "field V191._lower (fldOffset=0x0)" P-INDEP ;* V399 tmp388 [V399 ] ( 0, 0 ) long -> zero-ref "field V191._upper (fldOffset=0x8)" P-INDEP ;* V400 tmp389 [V400 ] ( 0, 0 ) long -> zero-ref "field V194._lower (fldOffset=0x0)" P-INDEP ; V401 tmp390 [V401,T36] ( 4, 8 ) long -> registers "field V194._upper (fldOffset=0x8)" P-INDEP ;* V402 tmp391 [V402 ] ( 0, 0 ) long -> zero-ref "field V196._lower (fldOffset=0x0)" P-INDEP ;* V403 tmp392 [V403 ] ( 0, 0 ) long -> zero-ref "field V196._upper (fldOffset=0x8)" P-INDEP ;* V404 tmp393 [V404 ] ( 0, 0 ) long -> zero-ref "field V199._lower (fldOffset=0x0)" P-INDEP -; V405 tmp394 [V405,T37] ( 4, 8 ) long -> rdx "field V199._upper (fldOffset=0x8)" P-INDEP +; V405 tmp394 [V405,T37] ( 4, 8 ) long -> r10 "field V199._upper (fldOffset=0x8)" P-INDEP ;* V406 tmp395 [V406 ] ( 0, 0 ) long -> zero-ref "field V201._lower (fldOffset=0x0)" P-INDEP ;* V407 tmp396 [V407 ] ( 0, 0 ) long -> zero-ref "field V201._upper (fldOffset=0x8)" P-INDEP ;* V408 tmp397 [V408 ] ( 0, 0 ) long -> zero-ref "field V204._lower (fldOffset=0x0)" P-INDEP ;* V409 tmp398 [V409 ] ( 0, 0 ) long -> zero-ref "field V204._upper (fldOffset=0x8)" P-INDEP ;* V410 tmp399 [V410 ] ( 0, 0 ) long -> zero-ref "field V206._lower (fldOffset=0x0)" P-INDEP ;* V411 tmp400 [V411 ] ( 0, 0 ) long -> zero-ref "field V206._upper (fldOffset=0x8)" P-INDEP -; V412 cse0 [V412,T12] ( 4, 16 ) long -> r15 "CSE #03: moderate" -; V413 cse1 [V413,T13] ( 4, 16 ) long -> r15 "CSE #05: moderate" +; V412 cse0 [V412,T12] ( 4, 16 ) long -> r11 "CSE #03: moderate" +; V413 cse1 [V413,T13] ( 4, 16 ) long -> rbx "CSE #05: moderate" ; V414 cse2 [V414,T14] ( 4, 16 ) long -> rbx "CSE #07: moderate" -; V415 cse3 [V415,T15] ( 4, 16 ) int -> r11 "CSE #02: moderate" -; V416 cse4 [V416,T16] ( 4, 16 ) int -> rbx "CSE #04: moderate" -; V417 cse5 [V417,T17] ( 4, 16 ) int -> r11 "CSE #06: moderate" +; V415 cse3 [V415,T15] ( 4, 16 ) int -> r10 "CSE #02: moderate" +; V416 cse4 [V416,T16] ( 4, 16 ) int -> r11 "CSE #04: moderate" +; V417 cse5 [V417,T17] ( 4, 16 ) int -> r10 "CSE #06: moderate" ; V418 cse6 [V418,T18] ( 4, 16 ) long -> r11 "CSE #01: moderate" ; V419 cse7 [V419,T19] ( 4, 15.84) long -> rsi "CSE #08: moderate" ; -; Lcl frame size = 32 +; Lcl frame size = 8 G_M34098_IG01: push rbp push r15 + push r14 push rbx - sub rsp, 32 - lea rbp, [rsp+0x30] - ;; size=13 bbWeight=1 PerfScore 3.75 + push rax + lea rbp, [rsp+0x20] + ;; size=12 bbWeight=1 PerfScore 5.50 G_M34098_IG02: - mov r9d, ecx + mov eax, ecx + xor r9d, r9d xor r10d, r10d - xor eax, eax - mov qword ptr [rbp-0x18], rax cmp ecx, 3 - jg SHORT G_M34098_IG10 - ;; size=17 bbWeight=1 PerfScore 3.00 + jg SHORT G_M34098_IG05 + ;; size=13 bbWeight=1 PerfScore 2.00 G_M34098_IG03: - mov bword ptr [rbp-0x28], rdx - jmp G_M34098_IG12 - align [0 bytes for IG05] + mov bword ptr [rbp-0x20], rdx + jmp G_M34098_IG07 + align [0 bytes for IG09] ;; size=9 bbWeight=0.50 PerfScore 1.50 G_M34098_IG04: - test r10d, r10d - jl G_M34098_IG15 - cmp ecx, esi - jg G_M34098_IG15 - ;; size=17 bbWeight=0.25 PerfScore 0.62 + mov rdx, bword ptr [rbp-0x20] + ;; size=4 bbWeight=2 PerfScore 2.00 G_M34098_IG05: - mov esi, r10d - mov r11, bword ptr [rbp-0x28] - mov rcx, qword ptr [r11+8*rsi] - mov rax, r8 - mul rdx:rax, rcx - mov rbx, qword ptr [rdi+8*rsi] - add rbx, rax - cmp rbx, rax - setb cl - movzx rcx, cl - add rcx, rdx - mov rdx, qword ptr [rbp-0x18] - lea r15, [rbx+rdx] - cmp r15, rbx + cmp r9d, eax + jae G_M34098_IG13 + mov r11d, r9d + mov bword ptr [rbp-0x20], rdx + mov rbx, qword ptr [rdx+8*r11] + mov rdx, r8 + mulx rbx, rdx, rbx + cmp r9d, esi + jae G_M34098_IG13 + mov r15, qword ptr [rdi+8*r11] + add r15, rdx + cmp r15, rdx setb dl movzx rdx, dl - add rdx, rcx - mov qword ptr [rdi+8*rsi], r15 - mov qword ptr [rbp-0x18], rdx - inc r10d - cmp r10d, r9d - mov bword ptr [rbp-0x28], r11 - jl SHORT G_M34098_IG05 - ;; size=76 bbWeight=3.96 PerfScore 68.31 + add rdx, rbx + add r10, r15 + cmp r10, r15 + setb bl + movzx rbx, bl + add rbx, rdx + mov qword ptr [rdi+8*r11], r10 + lea r10d, [r9+0x01] + cmp r10d, eax + jae G_M34098_IG13 + mov r11d, r10d + mov rdx, bword ptr [rbp-0x20] + mov r15, qword ptr [rdx+8*r11] + mov rdx, r8 + mulx r15, rdx, r15 + cmp r10d, esi + jae G_M34098_IG13 + mov r10, qword ptr [rdi+8*r11] + add r10, rdx + cmp r10, rdx + setb dl + movzx rdx, dl + add rdx, r15 + add rbx, r10 + cmp rbx, r10 + setb r10b + movzx r10, r10b + add r10, rdx + mov qword ptr [rdi+8*r11], rbx + lea r11d, [r9+0x02] + cmp r11d, eax + jae G_M34098_IG13 + mov ebx, r11d + mov rdx, bword ptr [rbp-0x20] + mov r15, qword ptr [rdx+8*rbx] + mov rdx, r8 + mulx r15, rdx, r15 + cmp r11d, esi + jae G_M34098_IG13 + mov r11, qword ptr [rdi+8*rbx] + add r11, rdx + cmp r11, rdx + setb dl + movzx rdx, dl + add rdx, r15 + add r10, r11 + cmp r10, r11 + setb r11b + movzx r11, r11b + add r11, rdx + mov qword ptr [rdi+8*rbx], r10 + ;; size=237 bbWeight=4 PerfScore 184.00 G_M34098_IG06: - mov rdx, qword ptr [rbp-0x18] - ;; size=4 bbWeight=1.98 PerfScore 1.98 + lea r10d, [r9+0x03] + cmp r10d, eax + jae G_M34098_IG13 + mov ebx, r10d + mov rdx, bword ptr [rbp-0x20] + mov r15, qword ptr [rdx+8*rbx] + mov rdx, r8 + mulx r15, rdx, r15 + cmp r10d, esi + jae G_M34098_IG13 + mov r10, qword ptr [rdi+8*rbx] + add r10, rdx + cmp r10, rdx + setb dl + movzx rdx, dl + add rdx, r15 + add r11, r10 + cmp r11, r10 + setb r10b + movzx r10, r10b + add r10, rdx + mov qword ptr [rdi+8*rbx], r11 + add r9d, 4 + lea edx, [r9+0x03] + cmp edx, ecx + jl G_M34098_IG04 + ;; size=97 bbWeight=4 PerfScore 70.00 G_M34098_IG07: - mov rax, rdx - ;; size=3 bbWeight=1 PerfScore 0.25 + cmp r9d, ecx + jge SHORT G_M34098_IG10 + ;; size=5 bbWeight=0.50 PerfScore 0.62 G_M34098_IG08: - add rsp, 32 + test r9d, r9d + jl SHORT G_M34098_IG12 + cmp ecx, esi + jg SHORT G_M34098_IG12 + ;; size=9 bbWeight=0.25 PerfScore 0.62 +G_M34098_IG09: + mov esi, r9d + mov rdx, bword ptr [rbp-0x20] + mov rcx, qword ptr [rdx+8*rsi] + mov rdx, r8 + mulx r11, rcx, rcx + mov rbx, qword ptr [rdi+8*rsi] + add rbx, rcx + cmp rbx, rcx + setb dl + movzx rdx, dl + mov r15d, edx + add r11, r15 + lea r14, [rbx+r10] + cmp r14, rbx + setb r10b + movzx r10, r10b + add r10, r11 + mov qword ptr [rdi+8*rsi], r14 + inc r9d + cmp r9d, eax + jl SHORT G_M34098_IG09 + ;; size=71 bbWeight=3.96 PerfScore 57.42 +G_M34098_IG10: + mov rax, r10 + ;; size=3 bbWeight=1 PerfScore 0.25 +G_M34098_IG11: + add rsp, 8 pop rbx + pop r14 pop r15 pop rbp ret - ;; size=9 bbWeight=1 PerfScore 2.75 -G_M34098_IG09: - mov rdx, bword ptr [rbp-0x28] - ;; size=4 bbWeight=2 PerfScore 2.00 -G_M34098_IG10: - cmp r10d, r9d - jae G_M34098_IG16 - mov r11d, r10d - mov bword ptr [rbp-0x28], rdx - mov rbx, qword ptr [rdx+8*r11] - mov rax, r8 - mul rdx:rax, rbx - cmp r10d, esi - jae G_M34098_IG16 - mov rbx, qword ptr [rdi+8*r11] - add rbx, rax - cmp rbx, rax - setb al - movzx rax, al - add rax, rdx - mov rdx, qword ptr [rbp-0x18] - add rdx, rbx - cmp rdx, rbx - setb bl - movzx rbx, bl - add rbx, rax - mov qword ptr [rdi+8*r11], rdx - lea r11d, [r10+0x01] - cmp r11d, r9d - jae G_M34098_IG16 - mov r15d, r11d - mov rdx, bword ptr [rbp-0x28] - mov rax, qword ptr [rdx+8*r15] - mul rdx:rax, r8 - cmp r11d, esi - jae G_M34098_IG16 - mov r11, qword ptr [rdi+8*r15] - add r11, rax - cmp r11, rax - setb al - movzx rax, al - add rax, rdx - add rbx, r11 - cmp rbx, r11 - setb dl - movzx rdx, dl - mov r11d, edx - add r11, rax - mov qword ptr [rdi+8*r15], rbx - lea ebx, [r10+0x02] - cmp ebx, r9d - jae G_M34098_IG16 - mov r15d, ebx - mov rdx, bword ptr [rbp-0x28] - mov rax, qword ptr [rdx+8*r15] - mul rdx:rax, r8 - cmp ebx, esi - jae G_M34098_IG16 - mov rbx, qword ptr [rdi+8*r15] - add rbx, rax - cmp rbx, rax - setb al - movzx rax, al - add rax, rdx - add r11, rbx - cmp r11, rbx - setb dl - movzx rdx, dl - add rax, rdx - mov qword ptr [rbp-0x20], rax - ;; size=227 bbWeight=4 PerfScore 187.00 -G_M34098_IG11: - mov qword ptr [rdi+8*r15], r11 - lea r11d, [r10+0x03] - cmp r11d, r9d - jae G_M34098_IG16 - mov ebx, r11d - mov rdx, bword ptr [rbp-0x28] - mov r15, qword ptr [rdx+8*rbx] - mov rax, r8 - mul rdx:rax, r15 - cmp r11d, esi - jae G_M34098_IG16 - mov r11, qword ptr [rdi+8*rbx] - add r11, rax - cmp r11, rax - setb al - movzx rax, al - add rdx, rax - mov rax, qword ptr [rbp-0x20] - add rax, r11 - cmp rax, r11 - setb r11b - movzx r11, r11b - add rdx, r11 - mov qword ptr [rdi+8*rbx], rax - mov qword ptr [rbp-0x18], rdx - add r10d, 4 - lea eax, [r10+0x03] - cmp eax, ecx - jl G_M34098_IG09 - ;; size=107 bbWeight=4 PerfScore 82.00 + ;; size=11 bbWeight=1 PerfScore 3.25 G_M34098_IG12: - cmp r10d, ecx - jl G_M34098_IG04 - ;; size=9 bbWeight=0.50 PerfScore 0.62 + cmp r9d, eax + jae SHORT G_M34098_IG13 + mov edx, r9d + mov r11, bword ptr [rbp-0x20] + mov rdx, qword ptr [r11+8*rdx] + mulx rbx, rdx, r8 + cmp r9d, esi + jae SHORT G_M34098_IG13 + mov r15d, r9d + mov r14, qword ptr [rdi+8*r15] + lea r15, [rdx+r14] + cmp r15, rdx + setb dl + movzx rdx, dl + add rdx, rbx + lea r14, [r15+r10] + cmp r14, r15 + setb r10b + movzx r10, r10b + add r10, rdx + mov edx, r9d + mov qword ptr [rdi+8*rdx], r14 + inc r9d + cmp r9d, ecx + mov bword ptr [rbp-0x20], r11 + jl SHORT G_M34098_IG12 + jmp SHORT G_M34098_IG10 + ;; size=88 bbWeight=0.04 PerfScore 0.81 G_M34098_IG13: - mov rdx, qword ptr [rbp-0x18] - jmp G_M34098_IG07 - ;; size=9 bbWeight=0.25 PerfScore 0.75 -G_M34098_IG14: - mov qword ptr [rbp-0x18], rdx - ;; size=4 bbWeight=0.02 PerfScore 0.02 -G_M34098_IG15: - cmp r10d, r9d - jae SHORT G_M34098_IG16 - mov eax, r10d - mov r11, bword ptr [rbp-0x28] - mov rax, qword ptr [r11+8*rax] - mul rdx:rax, r8 - cmp r10d, esi - jae SHORT G_M34098_IG16 - mov ebx, r10d - mov rbx, qword ptr [rdi+8*rbx] - add rbx, rax - cmp rbx, rax - setb al - movzx rax, al - add rax, rdx - mov rdx, rax - mov rax, qword ptr [rbp-0x18] - lea r15, [rbx+rax] - cmp r15, rbx - setb al - movzx rax, al - add rdx, rax - mov eax, r10d - mov qword ptr [rdi+8*rax], r15 - inc r10d - cmp r10d, ecx - mov bword ptr [rbp-0x28], r11 - jl SHORT G_M34098_IG14 - jmp G_M34098_IG07 - ;; size=93 bbWeight=0.04 PerfScore 0.85 -G_M34098_IG16: call CORINFO_HELP_RNGCHKFAIL int3 ;; size=6 bbWeight=0 PerfScore 0.00 -; Total bytes of code 607, prolog size 13, PerfScore 355.41, instruction count 179, allocated bytes for code 611 (MethodHash=5e2e7acd) for method System.Numerics.BigIntegerCalculator:MulAdd1(System.Span`1[nuint],System.ReadOnlySpan`1[nuint],nuint):nuint (FullOpts) +; Total bytes of code 565, prolog size 12, PerfScore 327.98, instruction count 169, allocated bytes for code 565 (MethodHash=5e2e7acd) for method System.Numerics.BigIntegerCalculator:MulAdd1(System.Span`1[nuint],System.ReadOnlySpan`1[nuint],nuint):nuint (FullOpts) ; ============================================================ ```
-42 (-6.92 % of base) - System.Numerics.BigIntegerCalculator:MulAdd1(System.Span`1[nuint],System.ReadOnlySpan`1[nuint],nuint):nuint ```diff ; Assembly listing for method System.Numerics.BigIntegerCalculator:MulAdd1(System.Span`1[nuint],System.ReadOnlySpan`1[nuint],nuint):nuint (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rbp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 96 single block inlinees; 10 inlinees without PGO data ; Final local variable assignments ; ;* V00 arg0 [V00 ] ( 0, 0 ) struct (16) zero-ref multireg-arg ld-addr-op single-def ;* V01 arg1 [V01 ] ( 0, 0 ) struct (16) zero-ref multireg-arg ld-addr-op single-def ; V02 arg2 [V02,T02] ( 8, 22 ) long -> r8 single-def -; V03 loc0 [V03,T04] ( 7, 21 ) int -> r9 -; V04 loc1 [V04,T00] ( 24, 53.91) int -> r10 -; V05 loc2 [V05,T06] ( 8, 18 ) long -> [rbp-0x18] +; V03 loc0 [V03,T04] ( 7, 21 ) int -> rax +; V04 loc1 [V04,T00] ( 24, 53.91) int -> r9 +; V05 loc2 [V05,T06] ( 8, 18 ) long -> r10 ;* V06 loc3 [V06 ] ( 0, 0 ) struct (16) zero-ref ;* V07 loc4 [V07 ] ( 0, 0 ) struct (16) zero-ref ;* V08 loc5 [V08 ] ( 0, 0 ) struct (16) zero-ref ;* V09 loc6 [V09 ] ( 0, 0 ) struct (16) zero-ref ;* V10 loc7 [V10 ] ( 0, 0 ) struct (16) zero-ref ;* V11 loc8 [V11 ] ( 0, 0 ) long -> zero-ref ;# V12 OutArgs [V12 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ;* V13 tmp1 [V13 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V14 tmp2 [V14 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V15 tmp3 [V15 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V16 tmp4 [V16 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V17 tmp5 [V17 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V18 tmp6 [V18 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V19 tmp7 [V19 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V20 tmp8 [V20 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V21 tmp9 [V21 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V22 tmp10 [V22 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V23 tmp11 [V23 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V24 tmp12 [V24 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V25 tmp13 [V25 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V26 tmp14 [V26 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V27 tmp15 [V27 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V28 tmp16 [V28 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V29 tmp17 [V29 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V30 tmp18 [V30 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V31 tmp19 [V31 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V32 tmp20 [V32 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V33 tmp21 [V33 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V34 tmp22 [V34 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V35 tmp23 [V35 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V36 tmp24 [V36 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V37 tmp25 [V37 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V38 tmp26 [V38 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V39 tmp27 [V39 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V40 tmp28 [V40 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V41 tmp29 [V41 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V42 tmp30 [V42 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V43 tmp31 [V43 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V44 tmp32 [V44 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V45 tmp33 [V45 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V46 tmp34 [V46 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V47 tmp35 [V47 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V48 tmp36 [V48 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V49 tmp37 [V49 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V50 tmp38 [V50 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V51 tmp39 [V51 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V52 tmp40 [V52 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V53 tmp41 [V53 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V54 tmp42 [V54 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V55 tmp43 [V55 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V56 tmp44 [V56 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V57 tmp45 [V57 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V58 tmp46 [V58 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V59 tmp47 [V59 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V60 tmp48 [V60 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V61 tmp49 [V61 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V62 tmp50 [V62 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V63 tmp51 [V63 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V64 tmp52 [V64 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V65 tmp53 [V65 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V66 tmp54 [V66 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" -; V67 tmp55 [V67,T08] ( 4, 16 ) long -> rbx "Inline stloc first use temp" -; V68 tmp56 [V68,T38] ( 2, 8 ) long -> rax "Inline stloc first use temp" +; V67 tmp55 [V67,T08] ( 4, 16 ) long -> r15 "Inline stloc first use temp" +; V68 tmp56 [V68,T38] ( 2, 8 ) long -> rdx "Inline stloc first use temp" ;* V69 tmp57 [V69 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V70 tmp58 [V70 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V71 tmp59 [V71 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" -; V72 tmp60 [V72,T22] ( 3, 12 ) long -> rdx "Inline stloc first use temp" +; V72 tmp60 [V72,T22] ( 3, 12 ) long -> r10 "Inline stloc first use temp" ; V73 tmp61 [V73,T39] ( 2, 8 ) long -> rbx "Inline stloc first use temp" ;* V74 tmp62 [V74 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V75 tmp63 [V75 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V76 tmp64 [V76 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V77 tmp65 [V77 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V78 tmp66 [V78 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V79 tmp67 [V79 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V80 tmp68 [V80 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V81 tmp69 [V81 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V82 tmp70 [V82 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V83 tmp71 [V83 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V84 tmp72 [V84 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V85 tmp73 [V85 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V86 tmp74 [V86 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V87 tmp75 [V87 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V88 tmp76 [V88 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V89 tmp77 [V89 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" -; V90 tmp78 [V90,T09] ( 4, 16 ) long -> r11 "Inline stloc first use temp" -; V91 tmp79 [V91,T40] ( 2, 8 ) long -> rax "Inline stloc first use temp" +; V90 tmp78 [V90,T09] ( 4, 16 ) long -> r10 "Inline stloc first use temp" +; V91 tmp79 [V91,T40] ( 2, 8 ) long -> rdx "Inline stloc first use temp" ;* V92 tmp80 [V92 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V93 tmp81 [V93 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V94 tmp82 [V94 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V95 tmp83 [V95 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V96 tmp84 [V96 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V97 tmp85 [V97 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V98 tmp86 [V98 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V99 tmp87 [V99 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V100 tmp88 [V100 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V101 tmp89 [V101 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V102 tmp90 [V102 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V103 tmp91 [V103 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V104 tmp92 [V104,T23] ( 3, 12 ) long -> rbx "Inline stloc first use temp" -; V105 tmp93 [V105,T41] ( 2, 8 ) long -> r11 "Inline stloc first use temp" +; V105 tmp93 [V105,T41] ( 2, 8 ) long -> r10 "Inline stloc first use temp" ;* V106 tmp94 [V106 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V107 tmp95 [V107 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V108 tmp96 [V108 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V109 tmp97 [V109 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V110 tmp98 [V110 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V111 tmp99 [V111 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V112 tmp100 [V112 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V113 tmp101 [V113 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V114 tmp102 [V114 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V115 tmp103 [V115 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V116 tmp104 [V116 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V117 tmp105 [V117 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V118 tmp106 [V118 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V119 tmp107 [V119 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V120 tmp108 [V120 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V121 tmp109 [V121 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" -; V122 tmp110 [V122,T10] ( 4, 16 ) long -> rbx "Inline stloc first use temp" -; V123 tmp111 [V123,T42] ( 2, 8 ) long -> rax "Inline stloc first use temp" +; V122 tmp110 [V122,T10] ( 4, 16 ) long -> r11 "Inline stloc first use temp" +; V123 tmp111 [V123,T42] ( 2, 8 ) long -> rdx "Inline stloc first use temp" ;* V124 tmp112 [V124 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V125 tmp113 [V125 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V126 tmp114 [V126 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V127 tmp115 [V127 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V128 tmp116 [V128 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V129 tmp117 [V129 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V130 tmp118 [V130 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V131 tmp119 [V131 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V132 tmp120 [V132 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V133 tmp121 [V133 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V134 tmp122 [V134 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V135 tmp123 [V135 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" -; V136 tmp124 [V136,T24] ( 3, 12 ) long -> r11 "Inline stloc first use temp" -; V137 tmp125 [V137,T43] ( 2, 8 ) long -> rdx "Inline stloc first use temp" +; V136 tmp124 [V136,T24] ( 3, 12 ) long -> r10 "Inline stloc first use temp" +; V137 tmp125 [V137,T43] ( 2, 8 ) long -> r11 "Inline stloc first use temp" ;* V138 tmp126 [V138 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V139 tmp127 [V139 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V140 tmp128 [V140 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V141 tmp129 [V141 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V142 tmp130 [V142 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V143 tmp131 [V143 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V144 tmp132 [V144 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V145 tmp133 [V145 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V146 tmp134 [V146 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V147 tmp135 [V147 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V148 tmp136 [V148 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V149 tmp137 [V149 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V150 tmp138 [V150 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V151 tmp139 [V151 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V152 tmp140 [V152 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V153 tmp141 [V153 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" -; V154 tmp142 [V154,T11] ( 4, 16 ) long -> r11 "Inline stloc first use temp" -; V155 tmp143 [V155,T44] ( 2, 8 ) long -> rax "Inline stloc first use temp" +; V154 tmp142 [V154,T11] ( 4, 16 ) long -> r10 "Inline stloc first use temp" +; V155 tmp143 [V155,T44] ( 2, 8 ) long -> rdx "Inline stloc first use temp" ;* V156 tmp144 [V156 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V157 tmp145 [V157 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V158 tmp146 [V158 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V159 tmp147 [V159 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V160 tmp148 [V160 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V161 tmp149 [V161 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V162 tmp150 [V162 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V163 tmp151 [V163 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V164 tmp152 [V164 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V165 tmp153 [V165 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V166 tmp154 [V166 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V167 tmp155 [V167 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" -; V168 tmp156 [V168,T25] ( 3, 12 ) long -> rax "Inline stloc first use temp" -; V169 tmp157 [V169,T45] ( 2, 8 ) long -> r11 "Inline stloc first use temp" +; V168 tmp156 [V168,T25] ( 3, 12 ) long -> r11 "Inline stloc first use temp" +; V169 tmp157 [V169,T45] ( 2, 8 ) long -> r10 "Inline stloc first use temp" ;* V170 tmp158 [V170 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V171 tmp159 [V171 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V172 tmp160 [V172 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V173 tmp161 [V173 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V174 tmp162 [V174 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V175 tmp163 [V175 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V176 tmp164 [V176 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V177 tmp165 [V177 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V178 tmp166 [V178 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V179 tmp167 [V179 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V180 tmp168 [V180 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V181 tmp169 [V181 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V182 tmp170 [V182 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V183 tmp171 [V183 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V184 tmp172 [V184 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V185 tmp173 [V185 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V186 tmp174 [V186 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V187 tmp175 [V187 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V188 tmp176 [V188 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V189 tmp177 [V189 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V190 tmp178 [V190 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V191 tmp179 [V191 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V192 tmp180 [V192 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" -; V193 tmp181 [V193,T07] ( 8, 16 ) long -> rbx "Inline stloc first use temp" +; V193 tmp181 [V193,T07] ( 8, 16 ) long -> registers "Inline stloc first use temp" ; V194 tmp182 [V194,T31] ( 4, 8 ) long -> registers "Inline stloc first use temp" ;* V195 tmp183 [V195 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V196 tmp184 [V196 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V197 tmp185 [V197 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" -; V198 tmp186 [V198,T20] ( 6, 12 ) long -> r15 "Inline stloc first use temp" -; V199 tmp187 [V199,T32] ( 4, 8 ) long -> registers "Inline stloc first use temp" +; V198 tmp186 [V198,T20] ( 6, 12 ) long -> r14 "Inline stloc first use temp" +; V199 tmp187 [V199,T32] ( 4, 8 ) long -> r10 "Inline stloc first use temp" ;* V200 tmp188 [V200 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V201 tmp189 [V201 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V202 tmp190 [V202 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V203 tmp191 [V203 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V204 tmp192 [V204 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V205 tmp193 [V205 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V206 tmp194 [V206 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V207 tmp195 [V207 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V208 tmp196 [V208 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V209 tmp197 [V209,T01] ( 13, 41 ) byref -> rdi single-def "field V00._reference (fldOffset=0x0)" P-INDEP ; V210 tmp198 [V210,T05] ( 7, 17.29) int -> rsi single-def "field V00._length (fldOffset=0x8)" P-INDEP -; V211 tmp199 [V211,T03] ( 7, 21 ) byref -> [rbp-0x28] single-def "field V01._reference (fldOffset=0x0)" P-INDEP +; V211 tmp199 [V211,T03] ( 7, 21 ) byref -> [rbp-0x20] single-def "field V01._reference (fldOffset=0x0)" P-INDEP ; V212 tmp200 [V212,T30] ( 7, 7.79) int -> rcx single-def "field V01._length (fldOffset=0x8)" P-INDEP ;* V213 tmp201 [V213 ] ( 0, 0 ) long -> zero-ref "field V06._lower (fldOffset=0x0)" P-INDEP ;* V214 tmp202 [V214 ] ( 0, 0 ) long -> zero-ref "field V06._upper (fldOffset=0x8)" P-INDEP ;* V215 tmp203 [V215 ] ( 0, 0 ) long -> zero-ref "field V07._lower (fldOffset=0x0)" P-INDEP ;* V216 tmp204 [V216 ] ( 0, 0 ) long -> zero-ref "field V07._upper (fldOffset=0x8)" P-INDEP ;* V217 tmp205 [V217 ] ( 0, 0 ) long -> zero-ref "field V08._lower (fldOffset=0x0)" P-INDEP ;* V218 tmp206 [V218 ] ( 0, 0 ) long -> zero-ref "field V08._upper (fldOffset=0x8)" P-INDEP ;* V219 tmp207 [V219 ] ( 0, 0 ) long -> zero-ref "field V09._lower (fldOffset=0x0)" P-INDEP ;* V220 tmp208 [V220 ] ( 0, 0 ) long -> zero-ref "field V09._upper (fldOffset=0x8)" P-INDEP ;* V221 tmp209 [V221 ] ( 0, 0 ) long -> zero-ref "field V10._lower (fldOffset=0x0)" P-INDEP ;* V222 tmp210 [V222 ] ( 0, 0 ) long -> zero-ref "field V10._upper (fldOffset=0x8)" P-INDEP ;* V223 tmp211 [V223 ] ( 0, 0 ) long -> zero-ref "field V13._lower (fldOffset=0x0)" P-INDEP ;* V224 tmp212 [V224 ] ( 0, 0 ) long -> zero-ref "field V13._upper (fldOffset=0x8)" P-INDEP ;* V225 tmp213 [V225 ] ( 0, 0 ) long -> zero-ref "field V14._lower (fldOffset=0x0)" P-INDEP ;* V226 tmp214 [V226 ] ( 0, 0 ) long -> zero-ref "field V14._upper (fldOffset=0x8)" P-INDEP ;* V227 tmp215 [V227 ] ( 0, 0 ) long -> zero-ref "field V15._lower (fldOffset=0x0)" P-INDEP ;* V228 tmp216 [V228 ] ( 0, 0 ) long -> zero-ref "field V15._upper (fldOffset=0x8)" P-INDEP ;* V229 tmp217 [V229 ] ( 0, 0 ) long -> zero-ref "field V16._lower (fldOffset=0x0)" P-INDEP ;* V230 tmp218 [V230 ] ( 0, 0 ) long -> zero-ref "field V16._upper (fldOffset=0x8)" P-INDEP ;* V231 tmp219 [V231 ] ( 0, 0 ) long -> zero-ref "field V17._lower (fldOffset=0x0)" P-INDEP ;* V232 tmp220 [V232 ] ( 0, 0 ) long -> zero-ref "field V17._upper (fldOffset=0x8)" P-INDEP ;* V233 tmp221 [V233 ] ( 0, 0 ) long -> zero-ref "field V18._lower (fldOffset=0x0)" P-INDEP ;* V234 tmp222 [V234 ] ( 0, 0 ) long -> zero-ref "field V18._upper (fldOffset=0x8)" P-INDEP ;* V235 tmp223 [V235 ] ( 0, 0 ) long -> zero-ref "field V20._lower (fldOffset=0x0)" P-INDEP ;* V236 tmp224 [V236 ] ( 0, 0 ) long -> zero-ref "field V20._upper (fldOffset=0x8)" P-INDEP ;* V237 tmp225 [V237 ] ( 0, 0 ) long -> zero-ref "field V21._lower (fldOffset=0x0)" P-INDEP ;* V238 tmp226 [V238 ] ( 0, 0 ) long -> zero-ref "field V21._upper (fldOffset=0x8)" P-INDEP ;* V239 tmp227 [V239 ] ( 0, 0 ) long -> zero-ref "field V22._lower (fldOffset=0x0)" P-INDEP ;* V240 tmp228 [V240 ] ( 0, 0 ) long -> zero-ref "field V22._upper (fldOffset=0x8)" P-INDEP ;* V241 tmp229 [V241 ] ( 0, 0 ) long -> zero-ref "field V23._lower (fldOffset=0x0)" P-INDEP ;* V242 tmp230 [V242 ] ( 0, 0 ) long -> zero-ref "field V23._upper (fldOffset=0x8)" P-INDEP ;* V243 tmp231 [V243 ] ( 0, 0 ) long -> zero-ref "field V24._lower (fldOffset=0x0)" P-INDEP ;* V244 tmp232 [V244 ] ( 0, 0 ) long -> zero-ref "field V24._upper (fldOffset=0x8)" P-INDEP ;* V245 tmp233 [V245 ] ( 0, 0 ) long -> zero-ref "field V25._lower (fldOffset=0x0)" P-INDEP ;* V246 tmp234 [V246 ] ( 0, 0 ) long -> zero-ref "field V25._upper (fldOffset=0x8)" P-INDEP ;* V247 tmp235 [V247 ] ( 0, 0 ) long -> zero-ref "field V26._lower (fldOffset=0x0)" P-INDEP ;* V248 tmp236 [V248 ] ( 0, 0 ) long -> zero-ref "field V26._upper (fldOffset=0x8)" P-INDEP ;* V249 tmp237 [V249 ] ( 0, 0 ) long -> zero-ref "field V28._lower (fldOffset=0x0)" P-INDEP ;* V250 tmp238 [V250 ] ( 0, 0 ) long -> zero-ref "field V28._upper (fldOffset=0x8)" P-INDEP ;* V251 tmp239 [V251 ] ( 0, 0 ) long -> zero-ref "field V29._lower (fldOffset=0x0)" P-INDEP ;* V252 tmp240 [V252 ] ( 0, 0 ) long -> zero-ref "field V29._upper (fldOffset=0x8)" P-INDEP ;* V253 tmp241 [V253 ] ( 0, 0 ) long -> zero-ref "field V30._lower (fldOffset=0x0)" P-INDEP ;* V254 tmp242 [V254 ] ( 0, 0 ) long -> zero-ref "field V30._upper (fldOffset=0x8)" P-INDEP ;* V255 tmp243 [V255 ] ( 0, 0 ) long -> zero-ref "field V31._lower (fldOffset=0x0)" P-INDEP ;* V256 tmp244 [V256 ] ( 0, 0 ) long -> zero-ref "field V31._upper (fldOffset=0x8)" P-INDEP ;* V257 tmp245 [V257 ] ( 0, 0 ) long -> zero-ref "field V32._lower (fldOffset=0x0)" P-INDEP ;* V258 tmp246 [V258 ] ( 0, 0 ) long -> zero-ref "field V32._upper (fldOffset=0x8)" P-INDEP ;* V259 tmp247 [V259 ] ( 0, 0 ) long -> zero-ref "field V33._lower (fldOffset=0x0)" P-INDEP ;* V260 tmp248 [V260 ] ( 0, 0 ) long -> zero-ref "field V33._upper (fldOffset=0x8)" P-INDEP ;* V261 tmp249 [V261 ] ( 0, 0 ) long -> zero-ref "field V34._lower (fldOffset=0x0)" P-INDEP ;* V262 tmp250 [V262 ] ( 0, 0 ) long -> zero-ref "field V34._upper (fldOffset=0x8)" P-INDEP ;* V263 tmp251 [V263 ] ( 0, 0 ) long -> zero-ref "field V36._lower (fldOffset=0x0)" P-INDEP ;* V264 tmp252 [V264 ] ( 0, 0 ) long -> zero-ref "field V36._upper (fldOffset=0x8)" P-INDEP ;* V265 tmp253 [V265 ] ( 0, 0 ) long -> zero-ref "field V37._lower (fldOffset=0x0)" P-INDEP ;* V266 tmp254 [V266 ] ( 0, 0 ) long -> zero-ref "field V37._upper (fldOffset=0x8)" P-INDEP ;* V267 tmp255 [V267 ] ( 0, 0 ) long -> zero-ref "field V38._lower (fldOffset=0x0)" P-INDEP ;* V268 tmp256 [V268 ] ( 0, 0 ) long -> zero-ref "field V38._upper (fldOffset=0x8)" P-INDEP ;* V269 tmp257 [V269 ] ( 0, 0 ) long -> zero-ref "field V39._lower (fldOffset=0x0)" P-INDEP ;* V270 tmp258 [V270 ] ( 0, 0 ) long -> zero-ref "field V39._upper (fldOffset=0x8)" P-INDEP ;* V271 tmp259 [V271 ] ( 0, 0 ) long -> zero-ref "field V40._lower (fldOffset=0x0)" P-INDEP ;* V272 tmp260 [V272 ] ( 0, 0 ) long -> zero-ref "field V40._upper (fldOffset=0x8)" P-INDEP ;* V273 tmp261 [V273 ] ( 0, 0 ) long -> zero-ref "field V41._lower (fldOffset=0x0)" P-INDEP ;* V274 tmp262 [V274 ] ( 0, 0 ) long -> zero-ref "field V41._upper (fldOffset=0x8)" P-INDEP ;* V275 tmp263 [V275 ] ( 0, 0 ) long -> zero-ref "field V42._lower (fldOffset=0x0)" P-INDEP ;* V276 tmp264 [V276 ] ( 0, 0 ) long -> zero-ref "field V42._upper (fldOffset=0x8)" P-INDEP ;* V277 tmp265 [V277 ] ( 0, 0 ) long -> zero-ref "field V44._lower (fldOffset=0x0)" P-INDEP ;* V278 tmp266 [V278 ] ( 0, 0 ) long -> zero-ref "field V44._upper (fldOffset=0x8)" P-INDEP ;* V279 tmp267 [V279 ] ( 0, 0 ) long -> zero-ref "field V45._lower (fldOffset=0x0)" P-INDEP ;* V280 tmp268 [V280 ] ( 0, 0 ) long -> zero-ref "field V45._upper (fldOffset=0x8)" P-INDEP ;* V281 tmp269 [V281 ] ( 0, 0 ) long -> zero-ref "field V46._lower (fldOffset=0x0)" P-INDEP ;* V282 tmp270 [V282 ] ( 0, 0 ) long -> zero-ref "field V46._upper (fldOffset=0x8)" P-INDEP ;* V283 tmp271 [V283 ] ( 0, 0 ) long -> zero-ref "field V47._lower (fldOffset=0x0)" P-INDEP ;* V284 tmp272 [V284 ] ( 0, 0 ) long -> zero-ref "field V47._upper (fldOffset=0x8)" P-INDEP ;* V285 tmp273 [V285 ] ( 0, 0 ) long -> zero-ref "field V48._lower (fldOffset=0x0)" P-INDEP ;* V286 tmp274 [V286 ] ( 0, 0 ) long -> zero-ref "field V48._upper (fldOffset=0x8)" P-INDEP ;* V287 tmp275 [V287 ] ( 0, 0 ) long -> zero-ref "field V49._lower (fldOffset=0x0)" P-INDEP ;* V288 tmp276 [V288 ] ( 0, 0 ) long -> zero-ref "field V49._upper (fldOffset=0x8)" P-INDEP ;* V289 tmp277 [V289 ] ( 0, 0 ) long -> zero-ref "field V50._lower (fldOffset=0x0)" P-INDEP ;* V290 tmp278 [V290 ] ( 0, 0 ) long -> zero-ref "field V50._upper (fldOffset=0x8)" P-INDEP ;* V291 tmp279 [V291 ] ( 0, 0 ) long -> zero-ref "field V52._lower (fldOffset=0x0)" P-INDEP ;* V292 tmp280 [V292 ] ( 0, 0 ) long -> zero-ref "field V52._upper (fldOffset=0x8)" P-INDEP ; V293 tmp281 [V293,T46] ( 2, 8 ) long -> rbx "field V54._lower (fldOffset=0x0)" P-INDEP ;* V294 tmp282 [V294 ] ( 0, 0 ) long -> zero-ref "field V54._upper (fldOffset=0x8)" P-INDEP ;* V295 tmp283 [V295 ] ( 0, 0 ) long -> zero-ref "field V55._lower (fldOffset=0x0)" P-INDEP ;* V296 tmp284 [V296 ] ( 0, 0 ) long -> zero-ref "field V55._upper (fldOffset=0x8)" P-INDEP ;* V297 tmp285 [V297 ] ( 0, 0 ) long -> zero-ref "field V57._lower (fldOffset=0x0)" P-INDEP ;* V298 tmp286 [V298 ] ( 0, 0 ) long -> zero-ref "field V57._upper (fldOffset=0x8)" P-INDEP ;* V299 tmp287 [V299 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V61.Item1 (fldOffset=0x0)" P-DEP ;* V300 tmp288 [V300 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V61.Item2 (fldOffset=0x8)" P-DEP -; V301 tmp289 [V301,T26] ( 3, 12 ) long -> rax "field V62.Item1 (fldOffset=0x0)" P-INDEP -; V302 tmp290 [V302,T47] ( 2, 8 ) long -> rdx "field V62.Item2 (fldOffset=0x8)" P-INDEP -; V303 tmp291 [V303,T48] ( 2, 8 ) long -> rbx "field V66._lower (fldOffset=0x0)" P-INDEP +; V301 tmp289 [V301,T26] ( 3, 12 ) long -> rdx "field V62.Item1 (fldOffset=0x0)" P-INDEP +; V302 tmp290 [V302,T47] ( 2, 8 ) long -> rbx "field V62.Item2 (fldOffset=0x8)" P-INDEP +; V303 tmp291 [V303,T48] ( 2, 8 ) long -> r15 "field V66._lower (fldOffset=0x0)" P-INDEP ;* V304 tmp292 [V304 ] ( 0, 0 ) long -> zero-ref "field V66._upper (fldOffset=0x8)" P-INDEP ;* V305 tmp293 [V305 ] ( 0, 0 ) long -> zero-ref "field V69._lower (fldOffset=0x0)" P-INDEP -; V306 tmp294 [V306,T49] ( 2, 8 ) long -> rax "field V69._upper (fldOffset=0x8)" P-INDEP +; V306 tmp294 [V306,T49] ( 2, 8 ) long -> rdx "field V69._upper (fldOffset=0x8)" P-INDEP ;* V307 tmp295 [V307 ] ( 0, 0 ) long -> zero-ref "field V71._lower (fldOffset=0x0)" P-INDEP ;* V308 tmp296 [V308 ] ( 0, 0 ) long -> zero-ref "field V71._upper (fldOffset=0x8)" P-INDEP ;* V309 tmp297 [V309 ] ( 0, 0 ) long -> zero-ref "field V74._lower (fldOffset=0x0)" P-INDEP ; V310 tmp298 [V310,T50] ( 2, 8 ) long -> rbx "field V74._upper (fldOffset=0x8)" P-INDEP -; V311 tmp299 [V311,T51] ( 2, 8 ) long -> rax "field V77._lower (fldOffset=0x0)" P-INDEP +; V311 tmp299 [V311,T51] ( 2, 8 ) long -> r15 "field V77._lower (fldOffset=0x0)" P-INDEP ;* V312 tmp300 [V312 ] ( 0, 0 ) long -> zero-ref "field V77._upper (fldOffset=0x8)" P-INDEP ;* V313 tmp301 [V313 ] ( 0, 0 ) long -> zero-ref "field V78._lower (fldOffset=0x0)" P-INDEP ;* V314 tmp302 [V314 ] ( 0, 0 ) long -> zero-ref "field V78._upper (fldOffset=0x8)" P-INDEP ;* V315 tmp303 [V315 ] ( 0, 0 ) long -> zero-ref "field V80._lower (fldOffset=0x0)" P-INDEP ;* V316 tmp304 [V316 ] ( 0, 0 ) long -> zero-ref "field V80._upper (fldOffset=0x8)" P-INDEP ;* V317 tmp305 [V317 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V84.Item1 (fldOffset=0x0)" P-DEP ;* V318 tmp306 [V318 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V84.Item2 (fldOffset=0x8)" P-DEP -; V319 tmp307 [V319,T27] ( 3, 12 ) long -> rax "field V85.Item1 (fldOffset=0x0)" P-INDEP -; V320 tmp308 [V320,T52] ( 2, 8 ) long -> rdx "field V85.Item2 (fldOffset=0x8)" P-INDEP -; V321 tmp309 [V321,T53] ( 2, 8 ) long -> r11 "field V89._lower (fldOffset=0x0)" P-INDEP +; V319 tmp307 [V319,T27] ( 3, 12 ) long -> rdx "field V85.Item1 (fldOffset=0x0)" P-INDEP +; V320 tmp308 [V320,T52] ( 2, 8 ) long -> r15 "field V85.Item2 (fldOffset=0x8)" P-INDEP +; V321 tmp309 [V321,T53] ( 2, 8 ) long -> r10 "field V89._lower (fldOffset=0x0)" P-INDEP ;* V322 tmp310 [V322 ] ( 0, 0 ) long -> zero-ref "field V89._upper (fldOffset=0x8)" P-INDEP ;* V323 tmp311 [V323 ] ( 0, 0 ) long -> zero-ref "field V92._lower (fldOffset=0x0)" P-INDEP -; V324 tmp312 [V324,T54] ( 2, 8 ) long -> rax "field V92._upper (fldOffset=0x8)" P-INDEP +; V324 tmp312 [V324,T54] ( 2, 8 ) long -> rdx "field V92._upper (fldOffset=0x8)" P-INDEP ;* V325 tmp313 [V325 ] ( 0, 0 ) long -> zero-ref "field V94._lower (fldOffset=0x0)" P-INDEP ;* V326 tmp314 [V326 ] ( 0, 0 ) long -> zero-ref "field V94._upper (fldOffset=0x8)" P-INDEP ;* V327 tmp315 [V327 ] ( 0, 0 ) long -> zero-ref "field V97._lower (fldOffset=0x0)" P-INDEP ;* V328 tmp316 [V328 ] ( 0, 0 ) long -> zero-ref "field V97._upper (fldOffset=0x8)" P-INDEP ;* V329 tmp317 [V329 ] ( 0, 0 ) long -> zero-ref "field V99._lower (fldOffset=0x0)" P-INDEP ;* V330 tmp318 [V330 ] ( 0, 0 ) long -> zero-ref "field V99._upper (fldOffset=0x8)" P-INDEP ;* V331 tmp319 [V331 ] ( 0, 0 ) long -> zero-ref "field V102._lower (fldOffset=0x0)" P-INDEP ;* V332 tmp320 [V332 ] ( 0, 0 ) long -> zero-ref "field V102._upper (fldOffset=0x8)" P-INDEP ;* V333 tmp321 [V333 ] ( 0, 0 ) long -> zero-ref "field V106._lower (fldOffset=0x0)" P-INDEP -; V334 tmp322 [V334,T55] ( 2, 8 ) long -> r11 "field V106._upper (fldOffset=0x8)" P-INDEP -; V335 tmp323 [V335,T56] ( 2, 8 ) long -> rax "field V109._lower (fldOffset=0x0)" P-INDEP +; V334 tmp322 [V334,T55] ( 2, 8 ) long -> r10 "field V106._upper (fldOffset=0x8)" P-INDEP +; V335 tmp323 [V335,T56] ( 2, 8 ) long -> r15 "field V109._lower (fldOffset=0x0)" P-INDEP ;* V336 tmp324 [V336 ] ( 0, 0 ) long -> zero-ref "field V109._upper (fldOffset=0x8)" P-INDEP ;* V337 tmp325 [V337 ] ( 0, 0 ) long -> zero-ref "field V110._lower (fldOffset=0x0)" P-INDEP ;* V338 tmp326 [V338 ] ( 0, 0 ) long -> zero-ref "field V110._upper (fldOffset=0x8)" P-INDEP ;* V339 tmp327 [V339 ] ( 0, 0 ) long -> zero-ref "field V112._lower (fldOffset=0x0)" P-INDEP ;* V340 tmp328 [V340 ] ( 0, 0 ) long -> zero-ref "field V112._upper (fldOffset=0x8)" P-INDEP ;* V341 tmp329 [V341 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V116.Item1 (fldOffset=0x0)" P-DEP ;* V342 tmp330 [V342 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V116.Item2 (fldOffset=0x8)" P-DEP -; V343 tmp331 [V343,T28] ( 3, 12 ) long -> rax "field V117.Item1 (fldOffset=0x0)" P-INDEP -; V344 tmp332 [V344,T57] ( 2, 8 ) long -> rdx "field V117.Item2 (fldOffset=0x8)" P-INDEP -; V345 tmp333 [V345,T58] ( 2, 8 ) long -> rbx "field V121._lower (fldOffset=0x0)" P-INDEP +; V343 tmp331 [V343,T28] ( 3, 12 ) long -> rdx "field V117.Item1 (fldOffset=0x0)" P-INDEP +; V344 tmp332 [V344,T57] ( 2, 8 ) long -> r15 "field V117.Item2 (fldOffset=0x8)" P-INDEP +; V345 tmp333 [V345,T58] ( 2, 8 ) long -> r11 "field V121._lower (fldOffset=0x0)" P-INDEP ;* V346 tmp334 [V346 ] ( 0, 0 ) long -> zero-ref "field V121._upper (fldOffset=0x8)" P-INDEP ;* V347 tmp335 [V347 ] ( 0, 0 ) long -> zero-ref "field V124._lower (fldOffset=0x0)" P-INDEP -; V348 tmp336 [V348,T59] ( 2, 8 ) long -> rax "field V124._upper (fldOffset=0x8)" P-INDEP +; V348 tmp336 [V348,T59] ( 2, 8 ) long -> rdx "field V124._upper (fldOffset=0x8)" P-INDEP ;* V349 tmp337 [V349 ] ( 0, 0 ) long -> zero-ref "field V126._lower (fldOffset=0x0)" P-INDEP ;* V350 tmp338 [V350 ] ( 0, 0 ) long -> zero-ref "field V126._upper (fldOffset=0x8)" P-INDEP ;* V351 tmp339 [V351 ] ( 0, 0 ) long -> zero-ref "field V129._lower (fldOffset=0x0)" P-INDEP ;* V352 tmp340 [V352 ] ( 0, 0 ) long -> zero-ref "field V129._upper (fldOffset=0x8)" P-INDEP ;* V353 tmp341 [V353 ] ( 0, 0 ) long -> zero-ref "field V131._lower (fldOffset=0x0)" P-INDEP ;* V354 tmp342 [V354 ] ( 0, 0 ) long -> zero-ref "field V131._upper (fldOffset=0x8)" P-INDEP ;* V355 tmp343 [V355 ] ( 0, 0 ) long -> zero-ref "field V134._lower (fldOffset=0x0)" P-INDEP ;* V356 tmp344 [V356 ] ( 0, 0 ) long -> zero-ref "field V134._upper (fldOffset=0x8)" P-INDEP ;* V357 tmp345 [V357 ] ( 0, 0 ) long -> zero-ref "field V138._lower (fldOffset=0x0)" P-INDEP -; V358 tmp346 [V358,T60] ( 2, 8 ) long -> [rbp-0x20] spill-single-def "field V138._upper (fldOffset=0x8)" P-INDEP +; V358 tmp346 [V358,T60] ( 2, 8 ) long -> r11 "field V138._upper (fldOffset=0x8)" P-INDEP ; V359 tmp347 [V359,T61] ( 2, 8 ) long -> r15 "field V141._lower (fldOffset=0x0)" P-INDEP ;* V360 tmp348 [V360 ] ( 0, 0 ) long -> zero-ref "field V141._upper (fldOffset=0x8)" P-INDEP ;* V361 tmp349 [V361 ] ( 0, 0 ) long -> zero-ref "field V142._lower (fldOffset=0x0)" P-INDEP ;* V362 tmp350 [V362 ] ( 0, 0 ) long -> zero-ref "field V142._upper (fldOffset=0x8)" P-INDEP ;* V363 tmp351 [V363 ] ( 0, 0 ) long -> zero-ref "field V144._lower (fldOffset=0x0)" P-INDEP ;* V364 tmp352 [V364 ] ( 0, 0 ) long -> zero-ref "field V144._upper (fldOffset=0x8)" P-INDEP ;* V365 tmp353 [V365 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V148.Item1 (fldOffset=0x0)" P-DEP ;* V366 tmp354 [V366 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V148.Item2 (fldOffset=0x8)" P-DEP -; V367 tmp355 [V367,T29] ( 3, 12 ) long -> rax "field V149.Item1 (fldOffset=0x0)" P-INDEP -; V368 tmp356 [V368,T62] ( 2, 8 ) long -> rdx "field V149.Item2 (fldOffset=0x8)" P-INDEP -; V369 tmp357 [V369,T63] ( 2, 8 ) long -> r11 "field V153._lower (fldOffset=0x0)" P-INDEP +; V367 tmp355 [V367,T29] ( 3, 12 ) long -> rdx "field V149.Item1 (fldOffset=0x0)" P-INDEP +; V368 tmp356 [V368,T62] ( 2, 8 ) long -> r15 "field V149.Item2 (fldOffset=0x8)" P-INDEP +; V369 tmp357 [V369,T63] ( 2, 8 ) long -> r10 "field V153._lower (fldOffset=0x0)" P-INDEP ;* V370 tmp358 [V370 ] ( 0, 0 ) long -> zero-ref "field V153._upper (fldOffset=0x8)" P-INDEP ;* V371 tmp359 [V371 ] ( 0, 0 ) long -> zero-ref "field V156._lower (fldOffset=0x0)" P-INDEP ; V372 tmp360 [V372,T64] ( 2, 8 ) long -> rdx "field V156._upper (fldOffset=0x8)" P-INDEP ;* V373 tmp361 [V373 ] ( 0, 0 ) long -> zero-ref "field V158._lower (fldOffset=0x0)" P-INDEP ;* V374 tmp362 [V374 ] ( 0, 0 ) long -> zero-ref "field V158._upper (fldOffset=0x8)" P-INDEP ;* V375 tmp363 [V375 ] ( 0, 0 ) long -> zero-ref "field V161._lower (fldOffset=0x0)" P-INDEP ;* V376 tmp364 [V376 ] ( 0, 0 ) long -> zero-ref "field V161._upper (fldOffset=0x8)" P-INDEP ;* V377 tmp365 [V377 ] ( 0, 0 ) long -> zero-ref "field V163._lower (fldOffset=0x0)" P-INDEP ;* V378 tmp366 [V378 ] ( 0, 0 ) long -> zero-ref "field V163._upper (fldOffset=0x8)" P-INDEP ;* V379 tmp367 [V379 ] ( 0, 0 ) long -> zero-ref "field V166._lower (fldOffset=0x0)" P-INDEP ;* V380 tmp368 [V380 ] ( 0, 0 ) long -> zero-ref "field V166._upper (fldOffset=0x8)" P-INDEP ;* V381 tmp369 [V381 ] ( 0, 0 ) long -> zero-ref "field V170._lower (fldOffset=0x0)" P-INDEP -; V382 tmp370 [V382,T65] ( 2, 8 ) long -> rdx "field V170._upper (fldOffset=0x8)" P-INDEP +; V382 tmp370 [V382,T65] ( 2, 8 ) long -> r10 "field V170._upper (fldOffset=0x8)" P-INDEP ;* V383 tmp371 [V383 ] ( 0, 0 ) long -> zero-ref "field V172._lower (fldOffset=0x0)" P-INDEP ;* V384 tmp372 [V384 ] ( 0, 0 ) long -> zero-ref "field V172._upper (fldOffset=0x8)" P-INDEP ;* V385 tmp373 [V385 ] ( 0, 0 ) long -> zero-ref "field V175._lower (fldOffset=0x0)" P-INDEP ;* V386 tmp374 [V386 ] ( 0, 0 ) long -> zero-ref "field V175._upper (fldOffset=0x8)" P-INDEP ;* V387 tmp375 [V387 ] ( 0, 0 ) long -> zero-ref "field V177._lower (fldOffset=0x0)" P-INDEP ;* V388 tmp376 [V388 ] ( 0, 0 ) long -> zero-ref "field V177._upper (fldOffset=0x8)" P-INDEP ; V389 tmp377 [V389,T33] ( 4, 8 ) long -> registers "field V180._lower (fldOffset=0x0)" P-INDEP ;* V390 tmp378 [V390 ] ( 0, 0 ) long -> zero-ref "field V180._upper (fldOffset=0x8)" P-INDEP ;* V391 tmp379 [V391 ] ( 0, 0 ) long -> zero-ref "field V181._lower (fldOffset=0x0)" P-INDEP ;* V392 tmp380 [V392 ] ( 0, 0 ) long -> zero-ref "field V181._upper (fldOffset=0x8)" P-INDEP ;* V393 tmp381 [V393 ] ( 0, 0 ) long -> zero-ref "field V183._lower (fldOffset=0x0)" P-INDEP ;* V394 tmp382 [V394 ] ( 0, 0 ) long -> zero-ref "field V183._upper (fldOffset=0x8)" P-INDEP ;* V395 tmp383 [V395 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V187.Item1 (fldOffset=0x0)" P-DEP ;* V396 tmp384 [V396 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V187.Item2 (fldOffset=0x8)" P-DEP -; V397 tmp385 [V397,T21] ( 6, 12 ) long -> rax "field V188.Item1 (fldOffset=0x0)" P-INDEP -; V398 tmp386 [V398,T34] ( 4, 8 ) long -> rdx "field V188.Item2 (fldOffset=0x8)" P-INDEP -; V399 tmp387 [V399,T35] ( 4, 8 ) long -> rbx "field V192._lower (fldOffset=0x0)" P-INDEP +; V397 tmp385 [V397,T21] ( 6, 12 ) long -> registers "field V188.Item1 (fldOffset=0x0)" P-INDEP +; V398 tmp386 [V398,T34] ( 4, 8 ) long -> registers "field V188.Item2 (fldOffset=0x8)" P-INDEP +; V399 tmp387 [V399,T35] ( 4, 8 ) long -> registers "field V192._lower (fldOffset=0x0)" P-INDEP ;* V400 tmp388 [V400 ] ( 0, 0 ) long -> zero-ref "field V192._upper (fldOffset=0x8)" P-INDEP ;* V401 tmp389 [V401 ] ( 0, 0 ) long -> zero-ref "field V195._lower (fldOffset=0x0)" P-INDEP ; V402 tmp390 [V402,T36] ( 4, 8 ) long -> registers "field V195._upper (fldOffset=0x8)" P-INDEP ;* V403 tmp391 [V403 ] ( 0, 0 ) long -> zero-ref "field V197._lower (fldOffset=0x0)" P-INDEP ;* V404 tmp392 [V404 ] ( 0, 0 ) long -> zero-ref "field V197._upper (fldOffset=0x8)" P-INDEP ;* V405 tmp393 [V405 ] ( 0, 0 ) long -> zero-ref "field V200._lower (fldOffset=0x0)" P-INDEP -; V406 tmp394 [V406,T37] ( 4, 8 ) long -> rdx "field V200._upper (fldOffset=0x8)" P-INDEP +; V406 tmp394 [V406,T37] ( 4, 8 ) long -> r10 "field V200._upper (fldOffset=0x8)" P-INDEP ;* V407 tmp395 [V407 ] ( 0, 0 ) long -> zero-ref "field V202._lower (fldOffset=0x0)" P-INDEP ;* V408 tmp396 [V408 ] ( 0, 0 ) long -> zero-ref "field V202._upper (fldOffset=0x8)" P-INDEP ;* V409 tmp397 [V409 ] ( 0, 0 ) long -> zero-ref "field V205._lower (fldOffset=0x0)" P-INDEP ;* V410 tmp398 [V410 ] ( 0, 0 ) long -> zero-ref "field V205._upper (fldOffset=0x8)" P-INDEP ;* V411 tmp399 [V411 ] ( 0, 0 ) long -> zero-ref "field V207._lower (fldOffset=0x0)" P-INDEP ;* V412 tmp400 [V412 ] ( 0, 0 ) long -> zero-ref "field V207._upper (fldOffset=0x8)" P-INDEP -; V413 cse0 [V413,T12] ( 4, 16 ) long -> r15 "CSE #03: moderate" -; V414 cse1 [V414,T13] ( 4, 16 ) long -> r15 "CSE #05: moderate" +; V413 cse0 [V413,T12] ( 4, 16 ) long -> r11 "CSE #03: moderate" +; V414 cse1 [V414,T13] ( 4, 16 ) long -> rbx "CSE #05: moderate" ; V415 cse2 [V415,T14] ( 4, 16 ) long -> rbx "CSE #07: moderate" -; V416 cse3 [V416,T15] ( 4, 16 ) int -> r11 "CSE #02: moderate" -; V417 cse4 [V417,T16] ( 4, 16 ) int -> rbx "CSE #04: moderate" -; V418 cse5 [V418,T17] ( 4, 16 ) int -> r11 "CSE #06: moderate" +; V416 cse3 [V416,T15] ( 4, 16 ) int -> r10 "CSE #02: moderate" +; V417 cse4 [V417,T16] ( 4, 16 ) int -> r11 "CSE #04: moderate" +; V418 cse5 [V418,T17] ( 4, 16 ) int -> r10 "CSE #06: moderate" ; V419 cse6 [V419,T18] ( 4, 16 ) long -> r11 "CSE #01: moderate" ; V420 cse7 [V420,T19] ( 4, 15.84) long -> rsi "CSE #08: moderate" ; -; Lcl frame size = 32 +; Lcl frame size = 8 G_M34098_IG01: push rbp push r15 + push r14 push rbx - sub rsp, 32 - lea rbp, [rsp+0x30] - ;; size=13 bbWeight=1 PerfScore 3.75 + push rax + lea rbp, [rsp+0x20] + ;; size=12 bbWeight=1 PerfScore 5.50 G_M34098_IG02: - mov r9d, ecx + mov eax, ecx + xor r9d, r9d xor r10d, r10d - xor eax, eax - mov qword ptr [rbp-0x18], rax cmp ecx, 3 - jg SHORT G_M34098_IG10 - ;; size=17 bbWeight=1 PerfScore 3.00 + jg SHORT G_M34098_IG05 + ;; size=13 bbWeight=1 PerfScore 2.00 G_M34098_IG03: - mov bword ptr [rbp-0x28], rdx - jmp G_M34098_IG12 - align [0 bytes for IG05] + mov bword ptr [rbp-0x20], rdx + jmp G_M34098_IG07 + align [0 bytes for IG09] ;; size=9 bbWeight=0.50 PerfScore 1.50 G_M34098_IG04: - test r10d, r10d - jl G_M34098_IG15 - cmp ecx, esi - jg G_M34098_IG15 - ;; size=17 bbWeight=0.25 PerfScore 0.62 + mov rdx, bword ptr [rbp-0x20] + ;; size=4 bbWeight=2 PerfScore 2.00 G_M34098_IG05: - mov esi, r10d - mov r11, bword ptr [rbp-0x28] - mov rcx, qword ptr [r11+8*rsi] - mov rax, r8 - mul rdx:rax, rcx - mov rbx, qword ptr [rdi+8*rsi] - add rbx, rax - cmp rbx, rax - setb cl - movzx rcx, cl - add rcx, rdx - mov rdx, qword ptr [rbp-0x18] - lea r15, [rbx+rdx] - cmp r15, rbx + cmp r9d, eax + jae G_M34098_IG13 + mov r11d, r9d + mov bword ptr [rbp-0x20], rdx + mov rbx, qword ptr [rdx+8*r11] + mov rdx, r8 + mulx rbx, rdx, rbx + cmp r9d, esi + jae G_M34098_IG13 + mov r15, qword ptr [rdi+8*r11] + add r15, rdx + cmp r15, rdx setb dl movzx rdx, dl - add rdx, rcx - mov qword ptr [rdi+8*rsi], r15 - mov qword ptr [rbp-0x18], rdx - inc r10d - cmp r10d, r9d - mov bword ptr [rbp-0x28], r11 - jl SHORT G_M34098_IG05 - ;; size=76 bbWeight=3.96 PerfScore 68.31 + add rdx, rbx + add r10, r15 + cmp r10, r15 + setb bl + movzx rbx, bl + add rbx, rdx + mov qword ptr [rdi+8*r11], r10 + lea r10d, [r9+0x01] + cmp r10d, eax + jae G_M34098_IG13 + mov r11d, r10d + mov rdx, bword ptr [rbp-0x20] + mov r15, qword ptr [rdx+8*r11] + mov rdx, r8 + mulx r15, rdx, r15 + cmp r10d, esi + jae G_M34098_IG13 + mov r10, qword ptr [rdi+8*r11] + add r10, rdx + cmp r10, rdx + setb dl + movzx rdx, dl + add rdx, r15 + add rbx, r10 + cmp rbx, r10 + setb r10b + movzx r10, r10b + add r10, rdx + mov qword ptr [rdi+8*r11], rbx + lea r11d, [r9+0x02] + cmp r11d, eax + jae G_M34098_IG13 + mov ebx, r11d + mov rdx, bword ptr [rbp-0x20] + mov r15, qword ptr [rdx+8*rbx] + mov rdx, r8 + mulx r15, rdx, r15 + cmp r11d, esi + jae G_M34098_IG13 + mov r11, qword ptr [rdi+8*rbx] + add r11, rdx + cmp r11, rdx + setb dl + movzx rdx, dl + add rdx, r15 + add r10, r11 + cmp r10, r11 + setb r11b + movzx r11, r11b + add r11, rdx + mov qword ptr [rdi+8*rbx], r10 + ;; size=237 bbWeight=4 PerfScore 184.00 G_M34098_IG06: - mov rdx, qword ptr [rbp-0x18] - ;; size=4 bbWeight=1.98 PerfScore 1.98 + lea r10d, [r9+0x03] + cmp r10d, eax + jae G_M34098_IG13 + mov ebx, r10d + mov rdx, bword ptr [rbp-0x20] + mov r15, qword ptr [rdx+8*rbx] + mov rdx, r8 + mulx r15, rdx, r15 + cmp r10d, esi + jae G_M34098_IG13 + mov r10, qword ptr [rdi+8*rbx] + add r10, rdx + cmp r10, rdx + setb dl + movzx rdx, dl + add rdx, r15 + add r11, r10 + cmp r11, r10 + setb r10b + movzx r10, r10b + add r10, rdx + mov qword ptr [rdi+8*rbx], r11 + add r9d, 4 + lea edx, [r9+0x03] + cmp edx, ecx + jl G_M34098_IG04 + ;; size=97 bbWeight=4 PerfScore 70.00 G_M34098_IG07: - mov rax, rdx - ;; size=3 bbWeight=1 PerfScore 0.25 + cmp r9d, ecx + jge SHORT G_M34098_IG10 + ;; size=5 bbWeight=0.50 PerfScore 0.62 G_M34098_IG08: - add rsp, 32 + test r9d, r9d + jl SHORT G_M34098_IG12 + cmp ecx, esi + jg SHORT G_M34098_IG12 + ;; size=9 bbWeight=0.25 PerfScore 0.62 +G_M34098_IG09: + mov esi, r9d + mov rdx, bword ptr [rbp-0x20] + mov rcx, qword ptr [rdx+8*rsi] + mov rdx, r8 + mulx r11, rcx, rcx + mov rbx, qword ptr [rdi+8*rsi] + add rbx, rcx + cmp rbx, rcx + setb dl + movzx rdx, dl + mov r15d, edx + add r11, r15 + lea r14, [rbx+r10] + cmp r14, rbx + setb r10b + movzx r10, r10b + add r10, r11 + mov qword ptr [rdi+8*rsi], r14 + inc r9d + cmp r9d, eax + jl SHORT G_M34098_IG09 + ;; size=71 bbWeight=3.96 PerfScore 57.42 +G_M34098_IG10: + mov rax, r10 + ;; size=3 bbWeight=1 PerfScore 0.25 +G_M34098_IG11: + add rsp, 8 pop rbx + pop r14 pop r15 pop rbp ret - ;; size=9 bbWeight=1 PerfScore 2.75 -G_M34098_IG09: - mov rdx, bword ptr [rbp-0x28] - ;; size=4 bbWeight=2 PerfScore 2.00 -G_M34098_IG10: - cmp r10d, r9d - jae G_M34098_IG16 - mov r11d, r10d - mov bword ptr [rbp-0x28], rdx - mov rbx, qword ptr [rdx+8*r11] - mov rax, r8 - mul rdx:rax, rbx - cmp r10d, esi - jae G_M34098_IG16 - mov rbx, qword ptr [rdi+8*r11] - add rbx, rax - cmp rbx, rax - setb al - movzx rax, al - add rax, rdx - mov rdx, qword ptr [rbp-0x18] - add rdx, rbx - cmp rdx, rbx - setb bl - movzx rbx, bl - add rbx, rax - mov qword ptr [rdi+8*r11], rdx - lea r11d, [r10+0x01] - cmp r11d, r9d - jae G_M34098_IG16 - mov r15d, r11d - mov rdx, bword ptr [rbp-0x28] - mov rax, qword ptr [rdx+8*r15] - mul rdx:rax, r8 - cmp r11d, esi - jae G_M34098_IG16 - mov r11, qword ptr [rdi+8*r15] - add r11, rax - cmp r11, rax - setb al - movzx rax, al - add rax, rdx - add rbx, r11 - cmp rbx, r11 - setb dl - movzx rdx, dl - mov r11d, edx - add r11, rax - mov qword ptr [rdi+8*r15], rbx - lea ebx, [r10+0x02] - cmp ebx, r9d - jae G_M34098_IG16 - mov r15d, ebx - mov rdx, bword ptr [rbp-0x28] - mov rax, qword ptr [rdx+8*r15] - mul rdx:rax, r8 - cmp ebx, esi - jae G_M34098_IG16 - mov rbx, qword ptr [rdi+8*r15] - add rbx, rax - cmp rbx, rax - setb al - movzx rax, al - add rax, rdx - add r11, rbx - cmp r11, rbx - setb dl - movzx rdx, dl - add rax, rdx - mov qword ptr [rbp-0x20], rax - ;; size=227 bbWeight=4 PerfScore 187.00 -G_M34098_IG11: - mov qword ptr [rdi+8*r15], r11 - lea r11d, [r10+0x03] - cmp r11d, r9d - jae G_M34098_IG16 - mov ebx, r11d - mov rdx, bword ptr [rbp-0x28] - mov r15, qword ptr [rdx+8*rbx] - mov rax, r8 - mul rdx:rax, r15 - cmp r11d, esi - jae G_M34098_IG16 - mov r11, qword ptr [rdi+8*rbx] - add r11, rax - cmp r11, rax - setb al - movzx rax, al - add rdx, rax - mov rax, qword ptr [rbp-0x20] - add rax, r11 - cmp rax, r11 - setb r11b - movzx r11, r11b - add rdx, r11 - mov qword ptr [rdi+8*rbx], rax - mov qword ptr [rbp-0x18], rdx - add r10d, 4 - lea eax, [r10+0x03] - cmp eax, ecx - jl G_M34098_IG09 - ;; size=107 bbWeight=4 PerfScore 82.00 + ;; size=11 bbWeight=1 PerfScore 3.25 G_M34098_IG12: - cmp r10d, ecx - jl G_M34098_IG04 - ;; size=9 bbWeight=0.50 PerfScore 0.62 + cmp r9d, eax + jae SHORT G_M34098_IG13 + mov edx, r9d + mov r11, bword ptr [rbp-0x20] + mov rdx, qword ptr [r11+8*rdx] + mulx rbx, rdx, r8 + cmp r9d, esi + jae SHORT G_M34098_IG13 + mov r15d, r9d + mov r14, qword ptr [rdi+8*r15] + lea r15, [rdx+r14] + cmp r15, rdx + setb dl + movzx rdx, dl + add rdx, rbx + lea r14, [r15+r10] + cmp r14, r15 + setb r10b + movzx r10, r10b + add r10, rdx + mov edx, r9d + mov qword ptr [rdi+8*rdx], r14 + inc r9d + cmp r9d, ecx + mov bword ptr [rbp-0x20], r11 + jl SHORT G_M34098_IG12 + jmp SHORT G_M34098_IG10 + ;; size=88 bbWeight=0.04 PerfScore 0.81 G_M34098_IG13: - mov rdx, qword ptr [rbp-0x18] - jmp G_M34098_IG07 - ;; size=9 bbWeight=0.25 PerfScore 0.75 -G_M34098_IG14: - mov qword ptr [rbp-0x18], rdx - ;; size=4 bbWeight=0.02 PerfScore 0.02 -G_M34098_IG15: - cmp r10d, r9d - jae SHORT G_M34098_IG16 - mov eax, r10d - mov r11, bword ptr [rbp-0x28] - mov rax, qword ptr [r11+8*rax] - mul rdx:rax, r8 - cmp r10d, esi - jae SHORT G_M34098_IG16 - mov ebx, r10d - mov rbx, qword ptr [rdi+8*rbx] - add rbx, rax - cmp rbx, rax - setb al - movzx rax, al - add rax, rdx - mov rdx, rax - mov rax, qword ptr [rbp-0x18] - lea r15, [rbx+rax] - cmp r15, rbx - setb al - movzx rax, al - add rdx, rax - mov eax, r10d - mov qword ptr [rdi+8*rax], r15 - inc r10d - cmp r10d, ecx - mov bword ptr [rbp-0x28], r11 - jl SHORT G_M34098_IG14 - jmp G_M34098_IG07 - ;; size=93 bbWeight=0.04 PerfScore 0.85 -G_M34098_IG16: call CORINFO_HELP_RNGCHKFAIL int3 ;; size=6 bbWeight=0 PerfScore 0.00 -; Total bytes of code 607, prolog size 13, PerfScore 355.41, instruction count 179, allocated bytes for code 611 (MethodHash=5e2e7acd) for method System.Numerics.BigIntegerCalculator:MulAdd1(System.Span`1[nuint],System.ReadOnlySpan`1[nuint],nuint):nuint (FullOpts) +; Total bytes of code 565, prolog size 12, PerfScore 327.98, instruction count 169, allocated bytes for code 565 (MethodHash=5e2e7acd) for method System.Numerics.BigIntegerCalculator:MulAdd1(System.Span`1[nuint],System.ReadOnlySpan`1[nuint],nuint):nuint (FullOpts) ; ============================================================ ```
-38 (-21.23 % of base) - System.Number:ComputeProductApproximation(int,long,ulong):System.ValueTuple`2[ulong,ulong] ```diff ; Assembly listing for method System.Number:ComputeProductApproximation(int,long,ulong):System.ValueTuple`2[ulong,ulong] (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rbp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 3 single block inlinees; 2 inlinees without PGO data ; Final local variable assignments ; ; V00 arg0 [V00,T00] ( 4, 3.50) int -> rdi single-def ; V01 arg1 [V01,T02] ( 3, 3 ) long -> rsi single-def -; V02 arg2 [V02,T01] ( 4, 3.50) long -> [rbp-0x08] single-def -; V03 loc0 [V03,T04] ( 4, 3.50) int -> rcx -; V04 loc1 [V04,T03] ( 5, 4 ) long -> r8 -; V05 loc2 [V05,T05] ( 4, 3 ) long -> rsi ld-addr-op +; V02 arg2 [V02,T01] ( 4, 3.50) long -> rdx single-def +; V03 loc0 [V03,T04] ( 4, 3.50) int -> rax +; V04 loc1 [V04,T03] ( 5, 4 ) long -> r9 +; V05 loc2 [V05,T05] ( 4, 3 ) long -> r8 ld-addr-op ;* V06 loc3 [V06 ] ( 0, 0 ) long -> zero-ref ;* V07 loc4 [V07 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V08 loc5 [V08 ] ( 0, 0 ) long -> zero-ref ;* V09 loc6 [V09 ] ( 0, 0 ) long -> zero-ref ld-addr-op ;* V10 loc7 [V10 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;# V11 OutArgs [V11 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ; V12 tmp1 [V12,T06] ( 4, 3 ) long -> rdi ;* V13 tmp2 [V13 ] ( 0, 0 ) struct (16) zero-ref multireg-ret ld-addr-op "NewObj constructor temp" ;* V14 tmp3 [V14 ] ( 0, 0 ) struct (16) zero-ref "ReadOnlySpan for CreateSpan" ;* V15 tmp4 [V15 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V16 tmp5 [V16 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V17 tmp6 [V17 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V18 tmp7 [V18 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V19 tmp8 [V19 ] ( 0, 0 ) struct (16) zero-ref "ReadOnlySpan for CreateSpan" ;* V20 tmp9 [V20 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V21 tmp10 [V21 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V22 tmp11 [V22 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Return value temp for multireg return" ;* V23 tmp12 [V23 ] ( 0, 0 ) struct (16) zero-ref "Inline stloc first use temp" ;* V24 tmp13 [V24 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V25 tmp14 [V25 ] ( 0, 0 ) byref -> zero-ref single-def "field V07._reference (fldOffset=0x0)" P-INDEP ;* V26 tmp15 [V26 ] ( 0, 0 ) int -> zero-ref "field V07._length (fldOffset=0x8)" P-INDEP ;* V27 tmp16 [V27 ] ( 0, 0 ) byref -> zero-ref single-def "field V10._reference (fldOffset=0x0)" P-INDEP ;* V28 tmp17 [V28 ] ( 0, 0 ) int -> zero-ref "field V10._length (fldOffset=0x8)" P-INDEP ;* V29 tmp18 [V29 ] ( 0, 0 ) long -> zero-ref "field V13.Item1 (fldOffset=0x0)" P-INDEP ;* V30 tmp19 [V30 ] ( 0, 0 ) long -> zero-ref "field V13.Item2 (fldOffset=0x8)" P-INDEP ;* V31 tmp20 [V31 ] ( 0, 0 ) byref -> zero-ref single-def "field V14._reference (fldOffset=0x0)" P-INDEP ;* V32 tmp21 [V32 ] ( 0, 0 ) int -> zero-ref "field V14._length (fldOffset=0x8)" P-INDEP ;* V33 tmp22 [V33 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V17.Item1 (fldOffset=0x0)" P-DEP ;* V34 tmp23 [V34 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V17.Item2 (fldOffset=0x8)" P-DEP -; V35 tmp24 [V35,T07] ( 3, 2.50) long -> [rbp-0x10] spill-single-def "field V18.Item1 (fldOffset=0x0)" P-INDEP -; V36 tmp25 [V36,T08] ( 3, 2.50) long -> [rbp-0x18] spill-single-def "field V18.Item2 (fldOffset=0x8)" P-INDEP +; V35 tmp24 [V35,T07] ( 3, 2.50) long -> rcx "field V18.Item1 (fldOffset=0x0)" P-INDEP +; V36 tmp25 [V36,T08] ( 3, 2.50) long -> rsi "field V18.Item2 (fldOffset=0x8)" P-INDEP ;* V37 tmp26 [V37 ] ( 0, 0 ) byref -> zero-ref single-def "field V19._reference (fldOffset=0x0)" P-INDEP ;* V38 tmp27 [V38 ] ( 0, 0 ) int -> zero-ref "field V19._length (fldOffset=0x8)" P-INDEP ; V39 tmp28 [V39,T11] ( 1, 0.50) long -> rax "field V22.Item1 (fldOffset=0x0)" P-INDEP ; V40 tmp29 [V40,T09] ( 3, 1.50) long -> rdx "field V22.Item2 (fldOffset=0x8)" P-INDEP ;* V41 tmp30 [V41 ] ( 0, 0 ) long -> zero-ref "field V23.Item1 (fldOffset=0x0)" P-INDEP ;* V42 tmp31 [V42 ] ( 0, 0 ) long -> zero-ref "field V23.Item2 (fldOffset=0x8)" P-INDEP -; V43 cse0 [V43,T10] ( 3, 1.50) int -> rcx "CSE #01: moderate" +; V43 cse0 [V43,T10] ( 3, 1.50) int -> rax "CSE #01: moderate" ; -; Lcl frame size = 32 +; Lcl frame size = 0 G_M1078_IG01: push rbp - sub rsp, 32 - lea rbp, [rsp+0x20] - mov rax, rdx - ;; size=13 bbWeight=1 PerfScore 2.00 + mov rbp, rsp + ;; size=4 bbWeight=1 PerfScore 1.25 G_M1078_IG02: - lea ecx, [2*rsi+0x2AC] - cmp ecx, 0x516 - jae G_M1078_IG09 - mov edx, ecx + lea eax, [2*rsi+0x2AC] + cmp eax, 0x516 + jae SHORT G_M1078_IG09 + mov ecx, eax mov rsi, 0xD1FFAB1E ; static handle - mov qword ptr [rbp-0x08], rax - mul rdx:rax, qword ptr [rsi+8*rdx] - mov qword ptr [rbp-0x10], rax - mov qword ptr [rbp-0x18], rdx - mov rsi, rax - mov r8, rdx + mulx rsi, rcx, qword ptr [rsi+8*rcx] + mov r8, rcx + mov r9, rsi cmp edi, 64 jge SHORT G_M1078_IG04 - ;; size=58 bbWeight=1 PerfScore 13.00 + ;; size=43 bbWeight=1 PerfScore 10.00 G_M1078_IG03: - mov r9, -1 - shrx rdi, r9, rdi + mov r10, -1 + shrx rdi, r10, rdi jmp SHORT G_M1078_IG05 ;; size=17 bbWeight=0.50 PerfScore 1.38 G_M1078_IG04: mov rdi, -1 ;; size=10 bbWeight=0.50 PerfScore 0.12 G_M1078_IG05: - mov r9, r8 - and r9, rdi - cmp r9, rdi + mov r10, r9 + and r10, rdi + cmp r10, rdi jne SHORT G_M1078_IG07 ;; size=11 bbWeight=1 PerfScore 1.75 G_M1078_IG06: - inc ecx - cmp ecx, 0x516 + inc eax + cmp eax, 0x516 jae SHORT G_M1078_IG09 - mov esi, ecx - mov rcx, 0xD1FFAB1E ; static handle - mov rax, qword ptr [rbp-0x08] - mul rdx:rax, qword ptr [rcx+8*rsi] - mov rax, qword ptr [rbp-0x10] - lea rsi, [rax+rdx] - mov rax, qword ptr [rbp-0x18] - inc rax - cmp rdx, rsi - cmova r8, rax - ;; size=52 bbWeight=0.50 PerfScore 6.25 + mov r8d, eax + mov rax, 0xD1FFAB1E ; static handle + mulx rdx, rax, qword ptr [rax+8*r8] + lea r8, [rcx+rdx] + inc rsi + cmp rdx, r8 + cmova r9, rsi + ;; size=42 bbWeight=0.50 PerfScore 4.75 G_M1078_IG07: - mov rax, r8 - mov rdx, rsi + mov rax, r9 + mov rdx, r8 ;; size=6 bbWeight=1 PerfScore 0.50 G_M1078_IG08: - add rsp, 32 pop rbp ret - ;; size=6 bbWeight=1 PerfScore 1.75 + ;; size=2 bbWeight=1 PerfScore 1.50 G_M1078_IG09: call CORINFO_HELP_RNGCHKFAIL int3 ;; size=6 bbWeight=0 PerfScore 0.00 -; Total bytes of code 179, prolog size 10, PerfScore 26.75, instruction count 45, allocated bytes for code 179 (MethodHash=9db2fbc9) for method System.Number:ComputeProductApproximation(int,long,ulong):System.ValueTuple`2[ulong,ulong] (FullOpts) +; Total bytes of code 141, prolog size 4, PerfScore 21.25, instruction count 36, allocated bytes for code 141 (MethodHash=9db2fbc9) for method System.Number:ComputeProductApproximation(int,long,ulong):System.ValueTuple`2[ulong,ulong] (FullOpts) ; ============================================================ ```
-32 (-2.25 % of base) - System.Decimal+DecCalc:DecAddSub(byref,byref,bool) ```diff ; Assembly listing for method System.Decimal+DecCalc:DecAddSub(byref,byref,bool) (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rbp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 60 single block inlinees; 8 inlinees without PGO data ; Final local variable assignments ; ; V00 arg0 [V00,T16] ( 11, 8 ) byref -> rbx single-def ; V01 arg1 [V01,T14] ( 14, 8.50) byref -> rsi single-def ; V02 arg2 [V02,T19] ( 8, 6 ) ubyte -> [rbp-0x2C] ; V03 loc0 [V03,T05] ( 40, 45 ) long -> r15 ld-addr-op ; V04 loc1 [V04,T06] ( 41, 35 ) int -> registers ; V05 loc2 [V05,T15] ( 18, 10 ) int -> registers ; V06 loc3 [V06,T37] ( 3, 2.50) int -> rax ; V07 loc4 [V07,T30] ( 3, 3 ) int -> rcx ; V08 loc5 [V08,T34] ( 5, 2.50) int -> r13 -; V09 loc6 [V09,T01] ( 25, 69.25) int -> [rbp-0x30] -; V10 loc7 [V10,T04] ( 10, 45.84) int -> rcx +; V09 loc6 [V09,T01] ( 25, 69.25) int -> rax +; V10 loc7 [V10,T04] ( 10, 45.84) int -> registers ; V11 loc8 [V11,T00] ( 17,104.20) long -> r14 ; V12 loc9 [V12 ] ( 24, 57.18) struct (24) [rbp-0x48] do-not-enreg[XSF] addr-exposed ld-addr-op ;* V13 loc10 [V13 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op -; V14 loc11 [V14,T09] ( 17, 22.50) int -> rax +; V14 loc11 [V14,T09] ( 17, 22.50) int -> rcx ; V15 loc12 [V15,T27] ( 7, 3.50) int -> rdx ; V16 loc13 [V16,T35] ( 5, 2.50) int -> rax ;* V17 loc14 [V17 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V18 loc15 [V18 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V19 loc16 [V19 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V20 loc17 [V20 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V21 loc18 [V21 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V22 loc19 [V22,T26] ( 0, 0 ) int -> zero-ref ; V23 loc20 [V23,T41] ( 3, 1.50) int -> rdx ; V24 loc21 [V24,T10] ( 15, 22.04) int -> rdx ; V25 loc22 [V25,T24] ( 9, 4.50) int -> rcx ; V26 loc23 [V26,T36] ( 5, 2.50) long -> rax ; V27 loc24 [V27,T28] ( 7, 3.50) int -> rcx ;# V28 OutArgs [V28 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ; V29 tmp1 [V29,T31] ( 3, 3 ) long -> rax "dup spill" ; V30 tmp2 [V30,T32] ( 3, 3 ) long -> rax "dup spill" ; V31 tmp3 [V31,T33] ( 3, 3 ) long -> rax "impAppendStmt" ; V32 tmp4 [V32,T38] ( 2, 2 ) long -> r15 "dup spill" -; V33 tmp5 [V33,T20] ( 2, 8 ) int -> rax "dup spill" +; V33 tmp5 [V33,T20] ( 2, 8 ) int -> rcx "dup spill" ; V34 tmp6 [V34,T07] ( 9, 27 ) byref -> rsi "dup spill" ; V35 tmp7 [V35,T29] ( 3, 3 ) byref -> rdx single-def "dup spill" -; V36 tmp8 [V36,T39] ( 2, 2 ) int -> rax "dup spill" +; V36 tmp8 [V36,T39] ( 2, 2 ) int -> rcx "dup spill" ; V37 tmp9 [V37,T12] ( 2, 16 ) int -> rax "dup spill" ; V38 tmp10 [V38,T40] ( 2, 2 ) int -> r15 "impAppendStmt" ;* V39 tmp11 [V39 ] ( 0, 0 ) struct (16) zero-ref "ReadOnlySpan for CreateSpan" ;* V40 tmp12 [V40 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V41 tmp13 [V41 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V42 tmp14 [V42 ] ( 0, 0 ) struct (16) zero-ref "ReadOnlySpan for CreateSpan" ;* V43 tmp15 [V43 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V44 tmp16 [V44 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V45 tmp17 [V45 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V46 tmp18 [V46 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V47 tmp19 [V47 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V48 tmp20 [V48 ] ( 0, 0 ) struct (16) zero-ref "ReadOnlySpan for CreateSpan" ;* V49 tmp21 [V49 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V50 tmp22 [V50 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V51 tmp23 [V51 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V52 tmp24 [V52 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V53 tmp25 [V53 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V54 tmp26 [V54 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V55 tmp27 [V55 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "Inline stloc first use temp" ;* V56 tmp28 [V56 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V57 tmp29 [V57 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V58 tmp30 [V58 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V59 tmp31 [V59 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V60 tmp32 [V60 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V61 tmp33 [V61 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "Inlining Arg" ;* V62 tmp34 [V62 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V63 tmp35 [V63 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V64 tmp36 [V64 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V65 tmp37 [V65 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ;* V66 tmp38 [V66 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "Inline stloc first use temp" ;* V67 tmp39 [V67 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V68 tmp40 [V68 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V69 tmp41 [V69 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V70 tmp42 [V70 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V71 tmp43 [V71 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "Inlining Arg" ;* V72 tmp44 [V72 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V73 tmp45 [V73 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V74 tmp46 [V74 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V75 tmp47 [V75 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ;* V76 tmp48 [V76 ] ( 0, 0 ) struct (16) zero-ref "ReadOnlySpan for CreateSpan" ; V77 tmp49 [V77,T08] ( 3, 24 ) int -> rdi "Inlining Arg" ;* V78 tmp50 [V78 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V79 tmp51 [V79 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ;* V80 tmp52 [V80 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V81 tmp53 [V81 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "Inline stloc first use temp" ;* V82 tmp54 [V82 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V83 tmp55 [V83 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V84 tmp56 [V84 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V85 tmp57 [V85 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V86 tmp58 [V86 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "Inlining Arg" ;* V87 tmp59 [V87 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V88 tmp60 [V88 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V89 tmp61 [V89 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V90 tmp62 [V90 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ;* V91 tmp63 [V91 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "Inline stloc first use temp" ;* V92 tmp64 [V92 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V93 tmp65 [V93 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V94 tmp66 [V94 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V95 tmp67 [V95 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V96 tmp68 [V96 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V97 tmp69 [V97 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "Inlining Arg" ;* V98 tmp70 [V98 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V99 tmp71 [V99 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V100 tmp72 [V100 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V101 tmp73 [V101 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ;* V102 tmp74 [V102 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "Inline stloc first use temp" ;* V103 tmp75 [V103 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V104 tmp76 [V104 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V105 tmp77 [V105 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V106 tmp78 [V106 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V107 tmp79 [V107 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "Inlining Arg" ;* V108 tmp80 [V108 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V109 tmp81 [V109 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V110 tmp82 [V110 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V111 tmp83 [V111 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ;* V112 tmp84 [V112 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V113 tmp85 [V113,T42] ( 0, 0 ) byref -> zero-ref single-def "field V13._reference (fldOffset=0x0)" P-INDEP ;* V114 tmp86 [V114,T49] ( 0, 0 ) int -> zero-ref "field V13._length (fldOffset=0x8)" P-INDEP ;* V115 tmp87 [V115 ] ( 0, 0 ) byref -> zero-ref "field V17._reference (fldOffset=0x0)" P-INDEP ;* V116 tmp88 [V116 ] ( 0, 0 ) int -> zero-ref "field V17._length (fldOffset=0x8)" P-INDEP ;* V117 tmp89 [V117 ] ( 0, 0 ) byref -> zero-ref "field V18._reference (fldOffset=0x0)" P-INDEP ;* V118 tmp90 [V118 ] ( 0, 0 ) int -> zero-ref "field V18._length (fldOffset=0x8)" P-INDEP ;* V119 tmp91 [V119 ] ( 0, 0 ) byref -> zero-ref "field V19._reference (fldOffset=0x0)" P-INDEP ;* V120 tmp92 [V120 ] ( 0, 0 ) int -> zero-ref "field V19._length (fldOffset=0x8)" P-INDEP ;* V121 tmp93 [V121,T25] ( 0, 0 ) byref -> zero-ref "field V20._reference (fldOffset=0x0)" P-INDEP ; V122 tmp94 [V122,T17] ( 3, 10 ) int -> rdi "field V20._length (fldOffset=0x8)" P-INDEP ;* V123 tmp95 [V123 ] ( 0, 0 ) byref -> zero-ref "field V21._reference (fldOffset=0x0)" P-INDEP ;* V124 tmp96 [V124 ] ( 0, 0 ) int -> zero-ref "field V21._length (fldOffset=0x8)" P-INDEP ;* V125 tmp97 [V125 ] ( 0, 0 ) byref -> zero-ref "field V39._reference (fldOffset=0x0)" P-INDEP ;* V126 tmp98 [V126 ] ( 0, 0 ) int -> zero-ref "field V39._length (fldOffset=0x8)" P-INDEP ;* V127 tmp99 [V127 ] ( 0, 0 ) byref -> zero-ref "field V42._reference (fldOffset=0x0)" P-INDEP ;* V128 tmp100 [V128 ] ( 0, 0 ) int -> zero-ref "field V42._length (fldOffset=0x8)" P-INDEP ;* V129 tmp101 [V129 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V46.Item1 (fldOffset=0x0)" P-DEP ;* V130 tmp102 [V130 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V46.Item2 (fldOffset=0x8)" P-DEP ; V131 tmp103 [V131,T21] ( 2, 8 ) long -> r15 "field V47.Item1 (fldOffset=0x0)" P-INDEP ; V132 tmp104 [V132,T22] ( 2, 8 ) long -> r14 "field V47.Item2 (fldOffset=0x8)" P-INDEP ;* V133 tmp105 [V133 ] ( 0, 0 ) byref -> zero-ref "field V48._reference (fldOffset=0x0)" P-INDEP ;* V134 tmp106 [V134 ] ( 0, 0 ) int -> zero-ref "field V48._length (fldOffset=0x8)" P-INDEP ;* V135 tmp107 [V135 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V52.Item1 (fldOffset=0x0)" P-DEP ;* V136 tmp108 [V136 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V52.Item2 (fldOffset=0x8)" P-DEP -; V137 tmp109 [V137,T18] ( 3, 8.50) long -> rax "field V53.Item1 (fldOffset=0x0)" P-INDEP -; V138 tmp110 [V138,T23] ( 2, 8 ) long -> rdx "field V53.Item2 (fldOffset=0x8)" P-INDEP +; V137 tmp109 [V137,T18] ( 3, 8.50) long -> rdx "field V53.Item1 (fldOffset=0x0)" P-INDEP +; V138 tmp110 [V138,T23] ( 2, 8 ) long -> rdi "field V53.Item2 (fldOffset=0x8)" P-INDEP ;* V139 tmp111 [V139,T43] ( 0, 0 ) byref -> zero-ref single-def "field V54._reference (fldOffset=0x0)" P-INDEP ;* V140 tmp112 [V140 ] ( 0, 0 ) int -> zero-ref "field V54._length (fldOffset=0x8)" P-INDEP ;* V141 tmp113 [V141 ] ( 0, 0 ) byref -> zero-ref single-def "field V55._reference (fldOffset=0x0)" P-INDEP ;* V142 tmp114 [V142 ] ( 0, 0 ) int -> zero-ref "field V55._length (fldOffset=0x8)" P-INDEP ;* V143 tmp115 [V143 ] ( 0, 0 ) byref -> zero-ref "field V57._reference (fldOffset=0x0)" P-INDEP ;* V144 tmp116 [V144 ] ( 0, 0 ) int -> zero-ref "field V57._length (fldOffset=0x8)" P-INDEP ;* V145 tmp117 [V145,T44] ( 0, 0 ) byref -> zero-ref single-def "field V58._reference (fldOffset=0x0)" P-INDEP ;* V146 tmp118 [V146 ] ( 0, 0 ) int -> zero-ref "field V58._length (fldOffset=0x8)" P-INDEP ;* V147 tmp119 [V147 ] ( 0, 0 ) byref -> zero-ref single-def "field V61._reference (fldOffset=0x0)" P-INDEP ;* V148 tmp120 [V148 ] ( 0, 0 ) int -> zero-ref "field V61._length (fldOffset=0x8)" P-INDEP ;* V149 tmp121 [V149 ] ( 0, 0 ) byref -> zero-ref single-def "field V64._reference (fldOffset=0x0)" P-INDEP ;* V150 tmp122 [V150 ] ( 0, 0 ) int -> zero-ref "field V64._length (fldOffset=0x8)" P-INDEP ;* V151 tmp123 [V151 ] ( 0, 0 ) byref -> zero-ref single-def "field V66._reference (fldOffset=0x0)" P-INDEP ;* V152 tmp124 [V152 ] ( 0, 0 ) int -> zero-ref "field V66._length (fldOffset=0x8)" P-INDEP ;* V153 tmp125 [V153 ] ( 0, 0 ) byref -> zero-ref "field V67._reference (fldOffset=0x0)" P-INDEP ;* V154 tmp126 [V154 ] ( 0, 0 ) int -> zero-ref "field V67._length (fldOffset=0x8)" P-INDEP ;* V155 tmp127 [V155,T45] ( 0, 0 ) byref -> zero-ref single-def "field V68._reference (fldOffset=0x0)" P-INDEP ;* V156 tmp128 [V156 ] ( 0, 0 ) int -> zero-ref "field V68._length (fldOffset=0x8)" P-INDEP ;* V157 tmp129 [V157 ] ( 0, 0 ) byref -> zero-ref single-def "field V71._reference (fldOffset=0x0)" P-INDEP ;* V158 tmp130 [V158 ] ( 0, 0 ) int -> zero-ref "field V71._length (fldOffset=0x8)" P-INDEP ;* V159 tmp131 [V159 ] ( 0, 0 ) byref -> zero-ref single-def "field V74._reference (fldOffset=0x0)" P-INDEP ;* V160 tmp132 [V160 ] ( 0, 0 ) int -> zero-ref "field V74._length (fldOffset=0x8)" P-INDEP ;* V161 tmp133 [V161 ] ( 0, 0 ) byref -> zero-ref "field V76._reference (fldOffset=0x0)" P-INDEP ;* V162 tmp134 [V162 ] ( 0, 0 ) int -> zero-ref "field V76._length (fldOffset=0x8)" P-INDEP ;* V163 tmp135 [V163 ] ( 0, 0 ) byref -> zero-ref "field V78._reference (fldOffset=0x0)" P-INDEP ;* V164 tmp136 [V164 ] ( 0, 0 ) int -> zero-ref "field V78._length (fldOffset=0x8)" P-INDEP ;* V165 tmp137 [V165 ] ( 0, 0 ) byref -> zero-ref single-def "field V81._reference (fldOffset=0x0)" P-INDEP ;* V166 tmp138 [V166 ] ( 0, 0 ) int -> zero-ref "field V81._length (fldOffset=0x8)" P-INDEP ;* V167 tmp139 [V167 ] ( 0, 0 ) byref -> zero-ref "field V82._reference (fldOffset=0x0)" P-INDEP ;* V168 tmp140 [V168 ] ( 0, 0 ) int -> zero-ref "field V82._length (fldOffset=0x8)" P-INDEP ;* V169 tmp141 [V169,T46] ( 0, 0 ) byref -> zero-ref single-def "field V83._reference (fldOffset=0x0)" P-INDEP ;* V170 tmp142 [V170 ] ( 0, 0 ) int -> zero-ref "field V83._length (fldOffset=0x8)" P-INDEP ;* V171 tmp143 [V171 ] ( 0, 0 ) byref -> zero-ref single-def "field V86._reference (fldOffset=0x0)" P-INDEP ;* V172 tmp144 [V172 ] ( 0, 0 ) int -> zero-ref "field V86._length (fldOffset=0x8)" P-INDEP ;* V173 tmp145 [V173 ] ( 0, 0 ) byref -> zero-ref single-def "field V89._reference (fldOffset=0x0)" P-INDEP ;* V174 tmp146 [V174 ] ( 0, 0 ) int -> zero-ref "field V89._length (fldOffset=0x8)" P-INDEP ;* V175 tmp147 [V175 ] ( 0, 0 ) byref -> zero-ref single-def "field V91._reference (fldOffset=0x0)" P-INDEP ;* V176 tmp148 [V176 ] ( 0, 0 ) int -> zero-ref "field V91._length (fldOffset=0x8)" P-INDEP ;* V177 tmp149 [V177 ] ( 0, 0 ) byref -> zero-ref "field V93._reference (fldOffset=0x0)" P-INDEP ;* V178 tmp150 [V178 ] ( 0, 0 ) int -> zero-ref "field V93._length (fldOffset=0x8)" P-INDEP ;* V179 tmp151 [V179,T47] ( 0, 0 ) byref -> zero-ref single-def "field V94._reference (fldOffset=0x0)" P-INDEP ;* V180 tmp152 [V180 ] ( 0, 0 ) int -> zero-ref "field V94._length (fldOffset=0x8)" P-INDEP ;* V181 tmp153 [V181 ] ( 0, 0 ) byref -> zero-ref single-def "field V97._reference (fldOffset=0x0)" P-INDEP ;* V182 tmp154 [V182 ] ( 0, 0 ) int -> zero-ref "field V97._length (fldOffset=0x8)" P-INDEP ;* V183 tmp155 [V183 ] ( 0, 0 ) byref -> zero-ref single-def "field V100._reference (fldOffset=0x0)" P-INDEP ;* V184 tmp156 [V184 ] ( 0, 0 ) int -> zero-ref "field V100._length (fldOffset=0x8)" P-INDEP ;* V185 tmp157 [V185 ] ( 0, 0 ) byref -> zero-ref single-def "field V102._reference (fldOffset=0x0)" P-INDEP ;* V186 tmp158 [V186 ] ( 0, 0 ) int -> zero-ref "field V102._length (fldOffset=0x8)" P-INDEP ;* V187 tmp159 [V187 ] ( 0, 0 ) byref -> zero-ref "field V103._reference (fldOffset=0x0)" P-INDEP ;* V188 tmp160 [V188 ] ( 0, 0 ) int -> zero-ref "field V103._length (fldOffset=0x8)" P-INDEP ;* V189 tmp161 [V189,T48] ( 0, 0 ) byref -> zero-ref single-def "field V104._reference (fldOffset=0x0)" P-INDEP ;* V190 tmp162 [V190 ] ( 0, 0 ) int -> zero-ref "field V104._length (fldOffset=0x8)" P-INDEP ;* V191 tmp163 [V191 ] ( 0, 0 ) byref -> zero-ref single-def "field V107._reference (fldOffset=0x0)" P-INDEP ;* V192 tmp164 [V192 ] ( 0, 0 ) int -> zero-ref "field V107._length (fldOffset=0x8)" P-INDEP ;* V193 tmp165 [V193 ] ( 0, 0 ) byref -> zero-ref single-def "field V110._reference (fldOffset=0x0)" P-INDEP ;* V194 tmp166 [V194 ] ( 0, 0 ) int -> zero-ref "field V110._length (fldOffset=0x8)" P-INDEP ;* V195 cse0 [V195,T13] ( 0, 0 ) long -> zero-ref "CSE #04: aggressive" ; V196 rat0 [V196,T02] ( 5, 65.36) long -> r8 "Strength reduced derived IV" ; V197 rat1 [V197,T03] ( 4, 49.52) int -> rdi "Trip count IV" ; V198 rat2 [V198,T11] ( 7, 21 ) long -> rsi "Widened IV V23" ; ; Lcl frame size = 40 G_M10604_IG01: push rbp push r15 push r14 push r13 push r12 push rbx sub rsp, 40 lea rbp, [rsp+0x50] mov rbx, rdi ;; size=22 bbWeight=1 PerfScore 7.00 G_M10604_IG02: mov r15, qword ptr [rbx+0x08] mov r14d, dword ptr [rbx+0x04] mov r13d, dword ptr [rbx] mov eax, dword ptr [rsi] mov ecx, eax xor ecx, r13d movzx rdx, dl test ecx, 0xD1FFAB1E setne dil movzx rdi, dil xor edx, edi test ecx, 0xD1FFAB1E - jne G_M10604_IG10 - ;; size=49 bbWeight=1 PerfScore 11.25 + jne SHORT G_M10604_IG04 + ;; size=45 bbWeight=1 PerfScore 11.25 G_M10604_IG03: mov dword ptr [rbp-0x2C], edx mov r12d, r13d - jmp SHORT G_M10604_IG06 - ;; size=8 bbWeight=0.50 PerfScore 1.62 + jmp G_M10604_IG10 + align [0 bytes for IG07] + ;; size=11 bbWeight=0.50 PerfScore 1.62 G_M10604_IG04: - mov dword ptr [rbp-0x30], eax - ;; size=3 bbWeight=2 PerfScore 2.00 -G_M10604_IG05: - mov edx, ecx - mov rax, rdx - mul rdx:rax, r15 - mov r15, rax - mov r14d, r14d - mov edi, ecx - imul r14, rdi - add r14, rdx - mov edx, dword ptr [rbp-0x30] - add edx, -9 - mov rcx, r14 - shr rcx, 32 - jne G_M10604_IG24 - test edx, edx - mov eax, edx - jg G_M10604_IG22 - ;; size=52 bbWeight=4 PerfScore 44.00 -G_M10604_IG06: - mov rax, r15 - mov ecx, r14d - cmp byte ptr [rbp-0x2C], 0 - je G_M10604_IG47 - mov r15, rax - sub r15, qword ptr [rsi+0x08] - mov r14d, ecx - sub r14d, dword ptr [rsi+0x04] - cmp r15, rax - jbe G_M10604_IG57 - dec r14d - cmp r14d, ecx - jb G_M10604_IG59 - ;; size=51 bbWeight=0.50 PerfScore 4.88 -G_M10604_IG07: - xor r12d, 0xD1FFAB1E - not r14d - neg r15 - jne G_M10604_IG60 - ;; size=19 bbWeight=0.50 PerfScore 0.88 -G_M10604_IG08: - inc r14d - mov edi, r14d - ;; size=6 bbWeight=0.50 PerfScore 0.25 -G_M10604_IG09: - mov dword ptr [rbx], r12d - mov dword ptr [rbx+0x04], edi - mov qword ptr [rbx+0x08], r15 - jmp G_M10604_IG62 - ;; size=15 bbWeight=0.50 PerfScore 2.50 -G_M10604_IG10: and eax, 0xD1FFAB1E mov ecx, r13d and ecx, 0xD1FFAB1E or ecx, eax mov r12d, ecx mov eax, r12d sub eax, r13d sar eax, 16 - jns SHORT G_M10604_IG11 + jns SHORT G_M10604_IG05 neg eax mov r12d, r13d xor r13d, 0xD1FFAB1E mov dword ptr [rbp-0x2C], edx test dl, dl cmovne r12d, r13d mov r15, qword ptr [rsi+0x08] mov r14d, dword ptr [rsi+0x04] vmovups xmm0, xmmword ptr [rbx] vmovups xmmword ptr [rsi], xmm0 movzx rdx, byte ptr [rbp-0x2C] ;; size=71 bbWeight=0.50 PerfScore 6.88 -G_M10604_IG11: +G_M10604_IG05: test r14d, r14d - je SHORT G_M10604_IG13 - ;; size=5 bbWeight=0.50 PerfScore 0.62 -G_M10604_IG12: + je G_M10604_IG14 + ;; size=9 bbWeight=0.50 PerfScore 0.62 +G_M10604_IG06: mov dword ptr [rbp-0x2C], edx - jmp G_M10604_IG22 - align [4 bytes for IG15] - ;; size=12 bbWeight=0.25 PerfScore 0.75 + ;; size=3 bbWeight=0.25 PerfScore 0.25 +G_M10604_IG07: + mov ecx, 0xD1FFAB1E + cmp eax, 9 + jae SHORT G_M10604_IG09 + ;; size=10 bbWeight=4 PerfScore 6.00 +G_M10604_IG08: + mov ecx, eax + mov rdx, 0xD1FFAB1E ; static handle + mov ecx, dword ptr [rdx+4*rcx] + ;; size=15 bbWeight=2 PerfScore 5.00 +G_M10604_IG09: + mov edi, ecx + mov rdx, rdi + mulx rdi, rdx, r15 + mov r15, rdx + mov r14d, r14d + mov r8d, ecx + imul r14, r8 + add r14, rdi + add eax, -9 + mov rcx, r14 + shr rcx, 32 + jne G_M10604_IG23 + test eax, eax + jg SHORT G_M10604_IG07 + ;; size=46 bbWeight=4 PerfScore 39.00 +G_M10604_IG10: + mov rax, r15 + mov ecx, r14d + cmp byte ptr [rbp-0x2C], 0 + je G_M10604_IG46 + mov r15, rax + sub r15, qword ptr [rsi+0x08] + mov r14d, ecx + sub r14d, dword ptr [rsi+0x04] + cmp r15, rax + jbe G_M10604_IG56 + dec r14d + cmp r14d, ecx + jb G_M10604_IG58 + ;; size=51 bbWeight=0.50 PerfScore 4.88 +G_M10604_IG11: + xor r12d, 0xD1FFAB1E + not r14d + neg r15 + jne G_M10604_IG59 + ;; size=19 bbWeight=0.50 PerfScore 0.88 +G_M10604_IG12: + inc r14d + mov edi, r14d + ;; size=6 bbWeight=0.50 PerfScore 0.25 G_M10604_IG13: + mov dword ptr [rbx], r12d + mov dword ptr [rbx+0x04], edi + mov qword ptr [rbx+0x08], r15 + jmp G_M10604_IG61 + align [2 bytes for IG16] + ;; size=17 bbWeight=0.50 PerfScore 2.50 +G_M10604_IG14: mov rcx, r15 shr rcx, 32 - jne SHORT G_M10604_IG18 + jne SHORT G_M10604_IG21 + ;; NOP compensation instructions of 4 bytes. test r15d, r15d - je G_M10604_IG61 - ;; size=18 bbWeight=0.50 PerfScore 1.50 -G_M10604_IG14: - cmp eax, 9 - jbe SHORT G_M10604_IG16 - ;; size=5 bbWeight=0.25 PerfScore 0.31 + je G_M10604_IG60 + ;; size=22 bbWeight=0.50 PerfScore 1.50 G_M10604_IG15: + cmp eax, 9 + jbe SHORT G_M10604_IG17 + ;; size=5 bbWeight=0.25 PerfScore 0.31 +G_M10604_IG16: add eax, -9 mov ecx, r15d imul r15, rcx, 0xD1FFAB1E mov rcx, r15 shr rcx, 32 - jne SHORT G_M10604_IG18 + jne SHORT G_M10604_IG21 cmp eax, 9 - ja SHORT G_M10604_IG15 + ja SHORT G_M10604_IG16 ;; size=27 bbWeight=4 PerfScore 22.00 -G_M10604_IG16: +G_M10604_IG17: mov r15d, r15d mov eax, eax mov rcx, 0xD1FFAB1E ; static handle mov eax, dword ptr [rcx+4*rax] imul r15, rax mov dword ptr [rbp-0x2C], edx - jmp G_M10604_IG06 - align [2 bytes for IG29] - ;; size=32 bbWeight=0.50 PerfScore 3.88 -G_M10604_IG17: - movzx rdx, byte ptr [rbp-0x2C] - ;; size=4 bbWeight=2 PerfScore 2.00 + jmp G_M10604_IG10 + align [0 bytes for IG28] + ;; size=30 bbWeight=0.50 PerfScore 3.88 G_M10604_IG18: - mov ecx, 0xD1FFAB1E - cmp eax, 9 - jb SHORT G_M10604_IG20 - ;; size=10 bbWeight=4 PerfScore 6.00 -G_M10604_IG19: - mov dword ptr [rbp-0x30], eax - mov dword ptr [rbp-0x2C], edx - jmp SHORT G_M10604_IG21 - ;; size=8 bbWeight=2 PerfScore 8.00 -G_M10604_IG20: - mov dword ptr [rbp-0x30], eax mov ecx, eax mov rdi, 0xD1FFAB1E ; static handle mov ecx, dword ptr [rdi+4*rcx] mov dword ptr [rbp-0x2C], edx - ;; size=21 bbWeight=2 PerfScore 9.00 -G_M10604_IG21: + ;; size=18 bbWeight=2 PerfScore 7.00 +G_M10604_IG19: mov ecx, ecx - mov rax, rcx - mul rdx:rax, r15 - mov r15, rax - mov r14, rdx - mov eax, dword ptr [rbp-0x30] + mov rdx, rcx + mulx r14, r15, r15 add eax, -9 test eax, eax - jle G_M10604_IG06 + jle G_M10604_IG10 test r14d, r14d - je SHORT G_M10604_IG17 - ;; size=33 bbWeight=4 PerfScore 31.00 -G_M10604_IG22: + jne G_M10604_IG07 + ;; size=30 bbWeight=4 PerfScore 25.00 +G_M10604_IG20: + movzx rdx, byte ptr [rbp-0x2C] + ;; size=4 bbWeight=2 PerfScore 2.00 +G_M10604_IG21: mov ecx, 0xD1FFAB1E cmp eax, 9 - jae G_M10604_IG04 - ;; size=14 bbWeight=4 PerfScore 6.00 -G_M10604_IG23: - mov dword ptr [rbp-0x30], eax - mov ecx, eax - mov rdx, 0xD1FFAB1E ; static handle - mov ecx, dword ptr [rdx+4*rcx] - jmp G_M10604_IG05 - ;; size=23 bbWeight=2 PerfScore 11.00 -G_M10604_IG24: - mov qword ptr [rbp-0x48], rax - mov qword ptr [rbp-0x40], r14 - mov eax, 3 - test edx, edx - jle G_M10604_IG33 - ;; size=21 bbWeight=0.50 PerfScore 1.75 -G_M10604_IG25: - mov ecx, 0xD1FFAB1E - cmp edx, 9 - jae SHORT G_M10604_IG27 + jb SHORT G_M10604_IG18 ;; size=10 bbWeight=4 PerfScore 6.00 -G_M10604_IG26: - mov ecx, edx +G_M10604_IG22: + mov dword ptr [rbp-0x2C], edx + jmp SHORT G_M10604_IG19 + ;; size=5 bbWeight=2 PerfScore 6.00 +G_M10604_IG23: + mov qword ptr [rbp-0x48], rdx + mov qword ptr [rbp-0x40], r14 + mov ecx, 3 + test eax, eax + jle G_M10604_IG32 + ;; size=21 bbWeight=0.50 PerfScore 1.75 +G_M10604_IG24: + mov edx, 0xD1FFAB1E + cmp eax, 9 + jae SHORT G_M10604_IG26 + ;; size=10 bbWeight=4 PerfScore 6.00 +G_M10604_IG25: + mov edx, eax mov rdi, 0xD1FFAB1E ; static handle - mov ecx, dword ptr [rdi+4*rcx] + mov edx, dword ptr [rdi+4*rdx] ;; size=15 bbWeight=2 PerfScore 5.00 -G_M10604_IG27: +G_M10604_IG26: xor r14d, r14d - lea edi, [rax+0x01] + lea edi, [rcx+0x01] cmp edi, 6 - ja G_M10604_IG63 + ja G_M10604_IG62 test edi, edi - je SHORT G_M10604_IG30 + je SHORT G_M10604_IG29 ;; size=19 bbWeight=4 PerfScore 13.00 -G_M10604_IG28: +G_M10604_IG27: xor r8d, r8d ;; size=3 bbWeight=2 PerfScore 0.50 -G_M10604_IG29: +G_M10604_IG28: lea r9, bword ptr [rbp-0x48] mov r9d, dword ptr [r9+r8] - mov r10d, ecx + mov r10d, edx imul r9, r10 add r9, r14 mov r14, r9 lea r9, bword ptr [rbp-0x48] mov dword ptr [r9+r8], r14d shr r14, 32 add r8, 4 dec edi - jne SHORT G_M10604_IG29 + jne SHORT G_M10604_IG28 ;; size=41 bbWeight=15.84 PerfScore 138.60 -G_M10604_IG30: +G_M10604_IG29: test r14d, r14d - je SHORT G_M10604_IG32 + je SHORT G_M10604_IG31 ;; size=5 bbWeight=4 PerfScore 5.00 -G_M10604_IG31: - inc eax - cmp eax, 6 +G_M10604_IG30: + inc ecx + cmp ecx, 6 + jae G_M10604_IG63 + cmp ecx, 6 jae G_M10604_IG64 - cmp eax, 6 - jae G_M10604_IG65 - lea rcx, bword ptr [rbp-0x48] - mov edi, eax - mov dword ptr [rcx+4*rdi], r14d + lea rdx, bword ptr [rbp-0x48] + mov edi, ecx + mov dword ptr [rdx+4*rdi], r14d ;; size=30 bbWeight=2 PerfScore 9.00 -G_M10604_IG32: - add edx, -9 - test edx, edx - jg G_M10604_IG25 +G_M10604_IG31: + add eax, -9 + test eax, eax + jg G_M10604_IG24 ;; size=11 bbWeight=4 PerfScore 6.00 -G_M10604_IG33: +G_M10604_IG32: mov r14, qword ptr [rbp-0x48] mov r15, qword ptr [rsi+0x08] mov edx, dword ptr [rbp-0x40] mov edi, dword ptr [rsi+0x04] cmp byte ptr [rbp-0x2C], 0 - jne G_M10604_IG41 + jne G_M10604_IG40 add r15, r14 add edi, edx cmp r15, r14 - jb SHORT G_M10604_IG34 + jb SHORT G_M10604_IG33 cmp edi, edx - jae SHORT G_M10604_IG37 - jmp SHORT G_M10604_IG35 + jae SHORT G_M10604_IG36 + jmp SHORT G_M10604_IG34 ;; size=40 bbWeight=0.50 PerfScore 6.50 -G_M10604_IG34: +G_M10604_IG33: inc edi cmp edi, edx - ja SHORT G_M10604_IG37 + ja SHORT G_M10604_IG36 ;; size=6 bbWeight=0.50 PerfScore 0.75 -G_M10604_IG35: +G_M10604_IG34: mov edx, 3 lea rsi, bword ptr [rbp-0x3C] inc dword ptr [rsi] cmp dword ptr [rbp-0x3C], 0 - jne SHORT G_M10604_IG37 - cmp eax, 6 - jge G_M10604_IG39 - align [1 bytes for IG36] + jne SHORT G_M10604_IG36 + cmp ecx, 6 + jge G_M10604_IG38 + align [1 bytes for IG35] ;; size=27 bbWeight=0.50 PerfScore 3.62 -G_M10604_IG36: +G_M10604_IG35: inc edx - cmp eax, edx - jl G_M10604_IG40 + cmp ecx, edx + jl G_M10604_IG39 lea rsi, bword ptr [rbp-0x48] - mov ecx, edx - lea rsi, bword ptr [rsi+4*rcx] + mov eax, edx + lea rsi, bword ptr [rsi+4*rax] inc dword ptr [rsi] lea rsi, bword ptr [rbp-0x48] - mov ecx, edx - cmp dword ptr [rsi+4*rcx], 0 - je SHORT G_M10604_IG36 + mov eax, edx + cmp dword ptr [rsi+4*rax], 0 + je SHORT G_M10604_IG35 ;; size=34 bbWeight=3.96 PerfScore 37.62 -G_M10604_IG37: +G_M10604_IG36: mov qword ptr [rbp-0x48], r15 mov dword ptr [rbp-0x40], edi mov edx, r12d shr edx, 16 movzx rdx, dl lea rdi, [rbp-0x48] - mov esi, eax + mov esi, ecx mov rax, 0xD1FFAB1E ; code for System.Decimal+DecCalc:ScaleResult(byref,int,int):int call [rax]System.Decimal+DecCalc:ScaleResult(byref,int,int):int shl eax, 16 and r12d, 0xD1FFAB1E or r12d, eax mov r15, qword ptr [rbp-0x48] mov edi, dword ptr [rbp-0x40] - jmp G_M10604_IG09 - align [7 bytes for IG44] + jmp G_M10604_IG13 + align [7 bytes for IG43] ;; size=66 bbWeight=0.50 PerfScore 6.00 -G_M10604_IG38: - cmp edx, 6 - jae G_M10604_IG65 - lea rsi, bword ptr [rbp-0x48] - mov ecx, edx - lea rsi, bword ptr [rsi+4*rcx] - inc dword ptr [rsi] - lea rsi, bword ptr [rbp-0x48] - mov ecx, edx - cmp dword ptr [rsi+4*rcx], 0 - jne SHORT G_M10604_IG37 - ;; size=33 bbWeight=0.04 PerfScore 0.37 -G_M10604_IG39: - inc edx - cmp eax, edx - jge SHORT G_M10604_IG38 - ;; size=6 bbWeight=0.04 PerfScore 0.06 -G_M10604_IG40: +G_M10604_IG37: cmp edx, 6 jae G_M10604_IG64 - lea rax, bword ptr [rbp-0x48] - mov esi, edx - mov dword ptr [rax+4*rsi], 1 + lea rsi, bword ptr [rbp-0x48] mov eax, edx - jmp G_M10604_IG37 + lea rsi, bword ptr [rsi+4*rax] + inc dword ptr [rsi] + lea rsi, bword ptr [rbp-0x48] + mov eax, edx + cmp dword ptr [rsi+4*rax], 0 + jne SHORT G_M10604_IG36 + ;; size=33 bbWeight=0.04 PerfScore 0.37 +G_M10604_IG38: + inc edx + cmp ecx, edx + jge SHORT G_M10604_IG37 + ;; size=6 bbWeight=0.04 PerfScore 0.06 +G_M10604_IG39: + cmp edx, 6 + jae G_M10604_IG63 + lea rcx, bword ptr [rbp-0x48] + mov esi, edx + mov dword ptr [rcx+4*rsi], 1 + mov ecx, edx + jmp G_M10604_IG36 ;; size=29 bbWeight=0.50 PerfScore 2.62 -G_M10604_IG41: +G_M10604_IG40: mov rsi, r14 sub rsi, r15 mov r15, rsi mov esi, edx sub esi, edi mov edi, esi cmp r15, r14 - ja SHORT G_M10604_IG42 + ja SHORT G_M10604_IG41 cmp edi, edx - jbe G_M10604_IG37 - jmp SHORT G_M10604_IG43 + jbe G_M10604_IG36 + jmp SHORT G_M10604_IG42 ;; size=30 bbWeight=0.50 PerfScore 3.00 -G_M10604_IG42: +G_M10604_IG41: dec edi cmp edi, edx - jb G_M10604_IG37 + jb G_M10604_IG36 ;; size=10 bbWeight=0.50 PerfScore 0.75 -G_M10604_IG43: +G_M10604_IG42: mov edx, 3 mov esi, 3 cmp dword ptr [rbp-0x3C], 0 - jne SHORT G_M10604_IG46 + jne SHORT G_M10604_IG45 ;; size=16 bbWeight=0.50 PerfScore 1.25 -G_M10604_IG44: +G_M10604_IG43: lea rdx, bword ptr [rbp-0x48] mov dword ptr [rdx+4*rsi], -1 inc esi cmp esi, 6 - jae G_M10604_IG65 + jae G_M10604_IG64 lea rdx, bword ptr [rbp-0x48] cmp dword ptr [rdx+4*rsi], 0 - je SHORT G_M10604_IG44 + je SHORT G_M10604_IG43 ;; size=32 bbWeight=4 PerfScore 26.00 -G_M10604_IG45: +G_M10604_IG44: mov edx, esi ;; size=2 bbWeight=0.50 PerfScore 0.12 -G_M10604_IG46: +G_M10604_IG45: lea rsi, bword ptr [rbp-0x48] mov edx, edx lea rdx, bword ptr [rsi+4*rdx] dec dword ptr [rdx] - cmp eax, 6 - jae G_M10604_IG65 + cmp ecx, 6 + jae G_M10604_IG64 lea rdx, bword ptr [rbp-0x48] - mov esi, eax + mov esi, ecx cmp dword ptr [rdx+4*rsi], 0 - jne G_M10604_IG37 - dec eax - cmp eax, 2 - jg G_M10604_IG37 - jmp G_M10604_IG09 + jne G_M10604_IG36 + dec ecx + cmp ecx, 2 + jg G_M10604_IG36 + jmp G_M10604_IG13 ;; size=53 bbWeight=0.50 PerfScore 6.38 -G_M10604_IG47: +G_M10604_IG46: mov r15, rax add r15, qword ptr [rsi+0x08] mov r14d, ecx add r14d, dword ptr [rsi+0x04] cmp r15, rax - jb SHORT G_M10604_IG49 + jb SHORT G_M10604_IG48 cmp r14d, ecx - jb SHORT G_M10604_IG51 + jb SHORT G_M10604_IG50 ;; size=24 bbWeight=0.50 PerfScore 3.50 -G_M10604_IG48: +G_M10604_IG47: mov edi, r14d - jmp G_M10604_IG09 + jmp G_M10604_IG13 ;; size=8 bbWeight=0.25 PerfScore 0.56 -G_M10604_IG49: +G_M10604_IG48: inc r14d cmp r14d, ecx - jbe SHORT G_M10604_IG51 + jbe SHORT G_M10604_IG50 ;; size=8 bbWeight=0.50 PerfScore 0.75 -G_M10604_IG50: +G_M10604_IG49: mov edi, r14d - jmp G_M10604_IG09 + jmp G_M10604_IG13 ;; size=8 bbWeight=0.25 PerfScore 0.56 -G_M10604_IG51: +G_M10604_IG50: test r12d, 0xD1FFAB1E - je G_M10604_IG64 + je G_M10604_IG63 add r12d, -0x10000 mov eax, r14d mov rcx, 0xD1FFAB1E add rax, rcx mov rdx, 0xD1FFAB1E mulx r14, r14, rax shr r14, 3 lea edx, [r14+4*r14] add edx, edx sub rax, rdx shl rax, 32 mov rcx, r15 shr rcx, 32 add rax, rcx mov rdx, 0xD1FFAB1E mulx rcx, rcx, rax shr rcx, 3 lea edx, [rcx+4*rcx] add edx, edx sub rax, rdx shl rax, 32 mov edi, r15d add rax, rdi mov r15d, ecx shl r15, 32 mov rdx, 0xD1FFAB1E mulx rcx, rcx, rax shr rcx, 3 mov edx, ecx add r15, rdx lea ecx, [rcx+4*rcx] add ecx, ecx sub eax, ecx mov ecx, eax cmp ecx, 5 - jae SHORT G_M10604_IG53 + jae SHORT G_M10604_IG52 ;; size=160 bbWeight=0.50 PerfScore 10.88 +G_M10604_IG51: + mov edi, r14d + jmp G_M10604_IG13 + ;; size=8 bbWeight=0.25 PerfScore 0.56 G_M10604_IG52: - mov edi, r14d - jmp G_M10604_IG09 - ;; size=8 bbWeight=0.25 PerfScore 0.56 -G_M10604_IG53: cmp ecx, 5 - ja SHORT G_M10604_IG55 + ja SHORT G_M10604_IG54 test r15b, 1 - jne SHORT G_M10604_IG55 + jne SHORT G_M10604_IG54 ;; size=11 bbWeight=0.50 PerfScore 1.25 +G_M10604_IG53: + mov edi, r14d + jmp G_M10604_IG13 + ;; size=8 bbWeight=0.25 PerfScore 0.56 G_M10604_IG54: - mov edi, r14d - jmp G_M10604_IG09 - ;; size=8 bbWeight=0.25 PerfScore 0.56 -G_M10604_IG55: inc r15 - je G_M10604_IG08 + je G_M10604_IG12 ;; size=9 bbWeight=0.50 PerfScore 0.62 -G_M10604_IG56: +G_M10604_IG55: mov edi, r14d - jmp G_M10604_IG09 + jmp G_M10604_IG13 ;; size=8 bbWeight=0.25 PerfScore 0.56 -G_M10604_IG57: +G_M10604_IG56: cmp r14d, ecx - ja G_M10604_IG07 + ja G_M10604_IG11 ;; size=9 bbWeight=0.50 PerfScore 0.62 +G_M10604_IG57: + mov edi, r14d + jmp G_M10604_IG13 + ;; size=8 bbWeight=0.25 PerfScore 0.56 G_M10604_IG58: mov edi, r14d - jmp G_M10604_IG09 + jmp G_M10604_IG13 ;; size=8 bbWeight=0.25 PerfScore 0.56 G_M10604_IG59: mov edi, r14d - jmp G_M10604_IG09 + jmp G_M10604_IG13 ;; size=8 bbWeight=0.25 PerfScore 0.56 G_M10604_IG60: - mov edi, r14d - jmp G_M10604_IG09 - ;; size=8 bbWeight=0.25 PerfScore 0.56 -G_M10604_IG61: mov eax, r12d and eax, 0xD1FFAB1E mov ecx, eax xor ecx, 0xD1FFAB1E test dl, dl cmovne eax, ecx vmovups xmm0, xmmword ptr [rsi] vmovups xmmword ptr [rbx], xmm0 mov ecx, dword ptr [rsi] and ecx, 0xD1FFAB1E or ecx, eax mov dword ptr [rbx], ecx ;; size=41 bbWeight=0.50 PerfScore 4.12 -G_M10604_IG62: +G_M10604_IG61: add rsp, 40 pop rbx pop r12 pop r13 pop r14 pop r15 pop rbp ret ;; size=15 bbWeight=1 PerfScore 4.25 -G_M10604_IG63: +G_M10604_IG62: mov rax, 0xD1FFAB1E ; code for System.ThrowHelper:ThrowArgumentOutOfRangeException() call [rax]System.ThrowHelper:ThrowArgumentOutOfRangeException() int3 ;; size=13 bbWeight=0 PerfScore 0.00 -G_M10604_IG64: +G_M10604_IG63: mov rax, 0xD1FFAB1E ; code for System.Number:ThrowDecimalOverflowException() call [rax]System.Number:ThrowDecimalOverflowException() int3 ;; size=13 bbWeight=0 PerfScore 0.00 -G_M10604_IG65: +G_M10604_IG64: call CORINFO_HELP_RNGCHKFAIL int3 ;; size=6 bbWeight=0 PerfScore 0.00 -; Total bytes of code 1420, prolog size 22, PerfScore 493.71, instruction count 400, allocated bytes for code 1420 (MethodHash=7e98d693) for method System.Decimal+DecCalc:DecAddSub(byref,byref,bool) (FullOpts) +; Total bytes of code 1388, prolog size 22, PerfScore 470.21, instruction count 390, allocated bytes for code 1388 (MethodHash=7e98d693) for method System.Decimal+DecCalc:DecAddSub(byref,byref,bool) (FullOpts) ; ============================================================ ```
-31 (-6.98 % of base) - System.IO.Hashing.XxHash3:HashLength0To16(ptr,uint,ulong):ulong ```diff ; Assembly listing for method System.IO.Hashing.XxHash3:HashLength0To16(ptr,uint,ulong):ulong (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rbp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 12 single block inlinees; 5 inlinees without PGO data ; Final local variable assignments ; ; V00 arg0 [V00,T04] ( 9, 5.50) long -> rdi single-def ; V01 arg1 [V01,T03] ( 10, 6.50) int -> rsi single-def ; V02 arg2 [V02,T05] ( 8, 5 ) long -> rdx single-def ;# V03 OutArgs [V03 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" -; V04 tmp1 [V04,T10] ( 2, 1 ) long -> rcx "Inline stloc first use temp" -; V05 tmp2 [V05,T11] ( 2, 1 ) long -> r8 "Inline stloc first use temp" -; V06 tmp3 [V06,T08] ( 3, 1.50) long -> rcx "Inline stloc first use temp" -; V07 tmp4 [V07,T09] ( 3, 1.50) long -> r8 "Inline stloc first use temp" +; V04 tmp1 [V04,T10] ( 2, 1 ) long -> rax "Inline stloc first use temp" +; V05 tmp2 [V05,T11] ( 2, 1 ) long -> rdx "Inline stloc first use temp" +; V06 tmp3 [V06,T08] ( 3, 1.50) long -> rax "Inline stloc first use temp" +; V07 tmp4 [V07,T09] ( 3, 1.50) long -> rdx "Inline stloc first use temp" ;* V08 tmp5 [V08 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V09 tmp6 [V09 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V10 tmp7 [V10 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V11 tmp8 [V11 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V12 tmp9 [V12 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V13 tmp10 [V13 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V14 tmp11 [V14 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V15 tmp12 [V15 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ; V16 tmp13 [V16,T06] ( 6, 6 ) long -> rax "Inlining Arg" ;* V17 tmp14 [V17 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V18 tmp15 [V18 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V19 tmp16 [V19 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V20 tmp17 [V20 ] ( 0, 0 ) int -> zero-ref "Inline return value spill temp" ;* V21 tmp18 [V21 ] ( 0, 0 ) int -> zero-ref "Inline return value spill temp" ;* V22 tmp19 [V22 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V23 tmp20 [V23,T00] ( 10, 10 ) long -> rax "Inlining Arg" ;* V24 tmp21 [V24 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp" ;* V25 tmp22 [V25 ] ( 0, 0 ) int -> zero-ref "impAppendStmt" ;* V26 tmp23 [V26 ] ( 0, 0 ) ubyte -> zero-ref "Inline stloc first use temp" ; V27 tmp24 [V27,T01] ( 9, 9 ) long -> rax "Inlining Arg" ; V28 tmp25 [V28,T02] ( 9, 9 ) long -> rax "Inlining Arg" ;* V29 tmp26 [V29 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V14.Item1 (fldOffset=0x0)" P-DEP ;* V30 tmp27 [V30 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V14.Item2 (fldOffset=0x8)" P-DEP -; V31 tmp28 [V31,T12] ( 2, 1 ) long -> rax "field V15.Item1 (fldOffset=0x0)" P-INDEP -; V32 tmp29 [V32,T13] ( 2, 1 ) long -> rdx "field V15.Item2 (fldOffset=0x8)" P-INDEP -; V33 cse0 [V33,T07] ( 6, 3 ) long -> [rbp-0x08] multi-def "CSE #01: aggressive" +; V31 tmp28 [V31,T12] ( 2, 1 ) long -> rdi "field V15.Item1 (fldOffset=0x0)" P-INDEP +; V32 tmp29 [V32,T13] ( 2, 1 ) long -> rsi "field V15.Item2 (fldOffset=0x8)" P-INDEP +; V33 cse0 [V33,T07] ( 6, 3 ) long -> rcx multi-def "CSE #01: aggressive" ; -; Lcl frame size = 16 +; Lcl frame size = 0 G_M20087_IG01: push rbp - sub rsp, 16 - lea rbp, [rsp+0x10] - ;; size=10 bbWeight=1 PerfScore 1.75 + mov rbp, rsp + ;; size=4 bbWeight=1 PerfScore 1.25 G_M20087_IG02: cmp esi, 8 ja G_M20087_IG09 ;; size=9 bbWeight=1 PerfScore 1.25 G_M20087_IG03: cmp esi, 4 jae G_M20087_IG07 test esi, esi jne SHORT G_M20087_IG05 mov rax, 0xD1FFAB1E xor rax, rdx mov rdi, rax shr rdi, 33 xor rdi, rax mov rax, 0xD1FFAB1E imul rax, rdi mov rsi, rax shr rsi, 29 xor rsi, rax mov rax, 0xD1FFAB1E imul rax, rsi mov rdx, rax shr rdx, 32 xor rax, rdx ;; size=84 bbWeight=0.50 PerfScore 5.25 G_M20087_IG04: - add rsp, 16 pop rbp ret - ;; size=6 bbWeight=0.50 PerfScore 0.88 + ;; size=2 bbWeight=0.50 PerfScore 0.75 G_M20087_IG05: movzx rax, byte ptr [rdi] shl eax, 16 mov ecx, esi shr ecx, 1 movzx rcx, byte ptr [rdi+rcx] shl ecx, 24 or eax, ecx lea ecx, [rsi-0x01] movzx rdi, byte ptr [rdi+rcx] or eax, edi shl esi, 8 or eax, esi mov ecx, 0xD1FFAB1E add rcx, rdx xor rax, rcx mov rdx, rax shr rdx, 33 xor rdx, rax mov rax, 0xD1FFAB1E imul rax, rdx mov rdx, rax shr rdx, 29 xor rdx, rax mov rax, 0xD1FFAB1E imul rax, rdx mov rdx, rax shr rdx, 32 xor rax, rdx ;; size=103 bbWeight=0.50 PerfScore 8.88 G_M20087_IG06: - add rsp, 16 pop rbp ret - ;; size=6 bbWeight=0.50 PerfScore 0.88 + ;; size=2 bbWeight=0.50 PerfScore 0.75 G_M20087_IG07: mov eax, edx bswap eax shl rax, 32 xor rax, rdx neg rax mov rdx, 0xD1FFAB1E add rax, rdx mov ecx, esi mov esi, dword ptr [rdi+rcx-0x04] mov edi, dword ptr [rdi] shl rdi, 32 add rdi, rsi xor rax, rdi rorx rdx, rax, 15 xor rdx, rax rol rax, 24 xor rax, rdx mov rdx, 0xD1FFAB1E imul rax, rdx mov rdx, rax shr rdx, 35 add rcx, rdx xor rcx, rax mov rax, 0xD1FFAB1E imul rax, rcx mov rdx, rax shr rdx, 28 xor rax, rdx ;; size=112 bbWeight=0.50 PerfScore 7.88 G_M20087_IG08: - add rsp, 16 pop rbp ret - ;; size=6 bbWeight=0.50 PerfScore 0.88 + ;; size=2 bbWeight=0.50 PerfScore 0.75 G_M20087_IG09: + mov rax, 0xD1FFAB1E + add rax, rdx + neg rdx mov rcx, 0xD1FFAB1E - add rcx, rdx - mov r8, rdx - neg r8 - mov r9, 0xD1FFAB1E - add r8, r9 - xor rcx, qword ptr [rdi] - mov eax, esi - mov qword ptr [rbp-0x08], rax - xor r8, qword ptr [rdi+rax-0x08] - mov rax, rcx - mul rdx:rax, r8 - bswap rcx - add rcx, qword ptr [rbp-0x08] - add rcx, r8 - xor rax, rdx + add rdx, rcx + xor rax, qword ptr [rdi] + mov ecx, esi + xor rdx, qword ptr [rdi+rcx-0x08] + mulx rsi, rdi, rax + bswap rax add rax, rcx + add rax, rdx + xor rdi, rsi + add rax, rdi mov rcx, rax shr rcx, 37 xor rcx, rax mov rax, 0xD1FFAB1E imul rax, rcx mov rcx, rax shr rcx, 32 xor rax, rcx - ;; size=102 bbWeight=0.50 PerfScore 8.50 + ;; size=93 bbWeight=0.50 PerfScore 7.38 G_M20087_IG10: - add rsp, 16 pop rbp ret - ;; size=6 bbWeight=0.50 PerfScore 0.88 + ;; size=2 bbWeight=0.50 PerfScore 0.75 -; Total bytes of code 444, prolog size 10, PerfScore 37.00, instruction count 117, allocated bytes for code 444 (MethodHash=64bbb188) for method System.IO.Hashing.XxHash3:HashLength0To16(ptr,uint,ulong):ulong (FullOpts) +; Total bytes of code 413, prolog size 4, PerfScore 34.88, instruction count 109, allocated bytes for code 413 (MethodHash=64bbb188) for method System.IO.Hashing.XxHash3:HashLength0To16(ptr,uint,ulong):ulong (FullOpts) ; ============================================================ ```
-30 (-21.58 % of base) - System.UInt128:BigMul(System.UInt128,System.UInt128,byref):System.UInt128 ```diff ; Assembly listing for method System.UInt128:BigMul(System.UInt128,System.UInt128,byref):System.UInt128 (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rbp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 25 single block inlinees; 4 inlinees without PGO data ; Final local variable assignments ; ;* V00 arg0 [V00 ] ( 0, 0 ) struct (16) zero-ref multireg-arg single-def ;* V01 arg1 [V01 ] ( 0, 0 ) struct (16) zero-ref multireg-arg single-def ; V02 arg2 [V02,T00] ( 4, 4 ) byref -> r8 single-def ;* V03 loc0 [V03 ] ( 0, 0 ) long -> zero-ref ;* V04 loc1 [V04 ] ( 0, 0 ) long -> zero-ref ;* V05 loc2 [V05 ] ( 0, 0 ) long -> zero-ref ;* V06 loc3 [V06 ] ( 0, 0 ) struct (16) zero-ref ;* V07 loc4 [V07 ] ( 0, 0 ) struct (16) zero-ref ;* V08 loc5 [V08 ] ( 0, 0 ) struct (16) zero-ref ;# V09 OutArgs [V09 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ;* V10 tmp1 [V10 ] ( 0, 0 ) long -> zero-ref "dup spill" ;* V11 tmp2 [V11 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V12 tmp3 [V12 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V13 tmp4 [V13 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V14 tmp5 [V14 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V15 tmp6 [V15 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V16 tmp7 [V16 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V17 tmp8 [V17 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V18 tmp9 [V18 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V19 tmp10 [V19 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V20 tmp11 [V20 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V21 tmp12 [V21 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V22 tmp13 [V22 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V23 tmp14 [V23 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V24 tmp15 [V24 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V25 tmp16 [V25 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V26 tmp17 [V26 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V27 tmp18 [V27 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V28 tmp19 [V28 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V29 tmp20 [V29 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V30 tmp21 [V30 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V31 tmp22 [V31 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V32 tmp23 [V32 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V33 tmp24 [V33 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V34 tmp25 [V34 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V35 tmp26 [V35 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V36 tmp27 [V36,T06] ( 3, 3 ) long -> r9 "Inline stloc first use temp" -; V37 tmp28 [V37,T12] ( 2, 2 ) long -> r10 "Inline stloc first use temp" +; V37 tmp28 [V37,T12] ( 2, 2 ) long -> r11 "Inline stloc first use temp" ;* V38 tmp29 [V38 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V39 tmp30 [V39 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V40 tmp31 [V40 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V41 tmp32 [V41 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V42 tmp33 [V42 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V43 tmp34 [V43 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V44 tmp35 [V44 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V45 tmp36 [V45 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V46 tmp37 [V46 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V47 tmp38 [V47 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V48 tmp39 [V48 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V49 tmp40 [V49,T07] ( 3, 3 ) long -> r9 "Inline stloc first use temp" -; V50 tmp41 [V50,T13] ( 2, 2 ) long -> rax "Inline stloc first use temp" +; V50 tmp41 [V50,T13] ( 2, 2 ) long -> r11 "Inline stloc first use temp" ;* V51 tmp42 [V51 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V52 tmp43 [V52 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V53 tmp44 [V53 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V54 tmp45 [V54 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V55 tmp46 [V55 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V56 tmp47 [V56 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V57 tmp48 [V57 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V58 tmp49 [V58 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V59 tmp50 [V59 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V60 tmp51 [V60 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V61 tmp52 [V61 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V62 tmp53 [V62 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V63 tmp54 [V63 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V64 tmp55 [V64,T05] ( 4, 4 ) long -> r10 "Inline stloc first use temp" ; V65 tmp56 [V65,T14] ( 2, 2 ) long -> rax "Inline stloc first use temp" ;* V66 tmp57 [V66 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V67 tmp58 [V67 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V68 tmp59 [V68 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V69 tmp60 [V69 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V70 tmp61 [V70 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V71 tmp62 [V71,T08] ( 3, 3 ) long -> rax "Inline stloc first use temp" ; V72 tmp63 [V72,T15] ( 2, 2 ) long -> rcx "Inline stloc first use temp" ;* V73 tmp64 [V73 ] ( 0, 0 ) struct (16) zero-ref multireg-ret ld-addr-op "NewObj constructor temp" ;* V74 tmp65 [V74 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V75 tmp66 [V75,T01] ( 3, 3 ) long -> rdi single-def "field V00._lower (fldOffset=0x0)" P-INDEP ; V76 tmp67 [V76,T02] ( 3, 3 ) long -> rsi single-def "field V00._upper (fldOffset=0x8)" P-INDEP -; V77 tmp68 [V77,T03] ( 3, 3 ) long -> [rbp-0x08] single-def "field V01._lower (fldOffset=0x0)" P-INDEP -; V78 tmp69 [V78,T04] ( 3, 3 ) long -> rcx single-def "field V01._upper (fldOffset=0x8)" P-INDEP +; V77 tmp68 [V77,T03] ( 3, 3 ) long -> rdx single-def "field V01._lower (fldOffset=0x0)" P-INDEP +; V78 tmp69 [V78,T04] ( 3, 3 ) long -> rax single-def "field V01._upper (fldOffset=0x8)" P-INDEP ;* V79 tmp70 [V79 ] ( 0, 0 ) long -> zero-ref "field V06._lower (fldOffset=0x0)" P-INDEP ;* V80 tmp71 [V80 ] ( 0, 0 ) long -> zero-ref "field V06._upper (fldOffset=0x8)" P-INDEP ;* V81 tmp72 [V81 ] ( 0, 0 ) long -> zero-ref "field V07._lower (fldOffset=0x0)" P-INDEP ;* V82 tmp73 [V82 ] ( 0, 0 ) long -> zero-ref "field V07._upper (fldOffset=0x8)" P-INDEP ;* V83 tmp74 [V83 ] ( 0, 0 ) long -> zero-ref "field V08._lower (fldOffset=0x0)" P-INDEP ;* V84 tmp75 [V84 ] ( 0, 0 ) long -> zero-ref "field V08._upper (fldOffset=0x8)" P-INDEP ;* V85 tmp76 [V85 ] ( 0, 0 ) long -> zero-ref "field V11._lower (fldOffset=0x0)" P-INDEP ;* V86 tmp77 [V86 ] ( 0, 0 ) long -> zero-ref "field V11._upper (fldOffset=0x8)" P-INDEP ;* V87 tmp78 [V87 ] ( 0, 0 ) long -> zero-ref "field V12._lower (fldOffset=0x0)" P-INDEP ;* V88 tmp79 [V88 ] ( 0, 0 ) long -> zero-ref "field V12._upper (fldOffset=0x8)" P-INDEP ;* V89 tmp80 [V89 ] ( 0, 0 ) long -> zero-ref "field V13._lower (fldOffset=0x0)" P-INDEP ;* V90 tmp81 [V90 ] ( 0, 0 ) long -> zero-ref "field V13._upper (fldOffset=0x8)" P-INDEP ;* V91 tmp82 [V91 ] ( 0, 0 ) long -> zero-ref "field V14._lower (fldOffset=0x0)" P-INDEP ;* V92 tmp83 [V92 ] ( 0, 0 ) long -> zero-ref "field V14._upper (fldOffset=0x8)" P-INDEP ;* V93 tmp84 [V93 ] ( 0, 0 ) long -> zero-ref "field V15._lower (fldOffset=0x0)" P-INDEP ;* V94 tmp85 [V94 ] ( 0, 0 ) long -> zero-ref "field V15._upper (fldOffset=0x8)" P-INDEP ;* V95 tmp86 [V95 ] ( 0, 0 ) long -> zero-ref "field V16._lower (fldOffset=0x0)" P-INDEP ;* V96 tmp87 [V96 ] ( 0, 0 ) long -> zero-ref "field V16._upper (fldOffset=0x8)" P-INDEP ;* V97 tmp88 [V97 ] ( 0, 0 ) long -> zero-ref "field V17._lower (fldOffset=0x0)" P-INDEP ;* V98 tmp89 [V98 ] ( 0, 0 ) long -> zero-ref "field V17._upper (fldOffset=0x8)" P-INDEP ;* V99 tmp90 [V99 ] ( 0, 0 ) long -> zero-ref "field V18._lower (fldOffset=0x0)" P-INDEP ;* V100 tmp91 [V100 ] ( 0, 0 ) long -> zero-ref "field V18._upper (fldOffset=0x8)" P-INDEP ;* V101 tmp92 [V101 ] ( 0, 0 ) long -> zero-ref "field V19._lower (fldOffset=0x0)" P-INDEP ;* V102 tmp93 [V102 ] ( 0, 0 ) long -> zero-ref "field V19._upper (fldOffset=0x8)" P-INDEP ;* V103 tmp94 [V103 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V20._lower (fldOffset=0x0)" P-DEP ;* V104 tmp95 [V104 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V20._upper (fldOffset=0x8)" P-DEP ;* V105 tmp96 [V105 ] ( 0, 0 ) long -> zero-ref "field V22._lower (fldOffset=0x0)" P-INDEP ;* V106 tmp97 [V106 ] ( 0, 0 ) long -> zero-ref "field V22._upper (fldOffset=0x8)" P-INDEP ;* V107 tmp98 [V107 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V24.Item1 (fldOffset=0x0)" P-DEP ;* V108 tmp99 [V108 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V24.Item2 (fldOffset=0x8)" P-DEP -; V109 tmp100 [V109,T16] ( 2, 2 ) long -> [rbp-0x10] spill-single-def "field V25.Item1 (fldOffset=0x0)" P-INDEP -; V110 tmp101 [V110,T17] ( 2, 2 ) long -> [rbp-0x18] spill-single-def "field V25.Item2 (fldOffset=0x8)" P-INDEP +; V109 tmp100 [V109,T16] ( 2, 2 ) long -> rcx "field V25.Item1 (fldOffset=0x0)" P-INDEP +; V110 tmp101 [V110,T17] ( 2, 2 ) long -> r9 "field V25.Item2 (fldOffset=0x8)" P-INDEP ;* V111 tmp102 [V111 ] ( 0, 0 ) long -> zero-ref "field V28._lower (fldOffset=0x0)" P-INDEP ;* V112 tmp103 [V112 ] ( 0, 0 ) long -> zero-ref "field V28._upper (fldOffset=0x8)" P-INDEP ;* V113 tmp104 [V113 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V30.Item1 (fldOffset=0x0)" P-DEP ;* V114 tmp105 [V114 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V30.Item2 (fldOffset=0x8)" P-DEP -; V115 tmp106 [V115,T09] ( 3, 3 ) long -> rax "field V31.Item1 (fldOffset=0x0)" P-INDEP -; V116 tmp107 [V116,T18] ( 2, 2 ) long -> rdx "field V31.Item2 (fldOffset=0x8)" P-INDEP +; V115 tmp106 [V115,T09] ( 3, 3 ) long -> rdx "field V31.Item1 (fldOffset=0x0)" P-INDEP +; V116 tmp107 [V116,T18] ( 2, 2 ) long -> r10 "field V31.Item2 (fldOffset=0x8)" P-INDEP ;* V117 tmp108 [V117 ] ( 0, 0 ) long -> zero-ref "field V34._lower (fldOffset=0x0)" P-INDEP ;* V118 tmp109 [V118 ] ( 0, 0 ) long -> zero-ref "field V34._upper (fldOffset=0x8)" P-INDEP ;* V119 tmp110 [V119 ] ( 0, 0 ) long -> zero-ref "field V38._lower (fldOffset=0x0)" P-INDEP ; V120 tmp111 [V120,T19] ( 2, 2 ) long -> r10 "field V38._upper (fldOffset=0x8)" P-INDEP ;* V121 tmp112 [V121 ] ( 0, 0 ) long -> zero-ref "field V41._lower (fldOffset=0x0)" P-INDEP ;* V122 tmp113 [V122 ] ( 0, 0 ) long -> zero-ref "field V41._upper (fldOffset=0x8)" P-INDEP ;* V123 tmp114 [V123 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V43.Item1 (fldOffset=0x0)" P-DEP ;* V124 tmp115 [V124 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V43.Item2 (fldOffset=0x8)" P-DEP -; V125 tmp116 [V125,T10] ( 3, 3 ) long -> rax "field V44.Item1 (fldOffset=0x0)" P-INDEP -; V126 tmp117 [V126,T20] ( 2, 2 ) long -> rdx "field V44.Item2 (fldOffset=0x8)" P-INDEP +; V125 tmp116 [V125,T10] ( 3, 3 ) long -> rdx "field V44.Item1 (fldOffset=0x0)" P-INDEP +; V126 tmp117 [V126,T20] ( 2, 2 ) long -> rdi "field V44.Item2 (fldOffset=0x8)" P-INDEP ;* V127 tmp118 [V127 ] ( 0, 0 ) long -> zero-ref "field V47._lower (fldOffset=0x0)" P-INDEP ;* V128 tmp119 [V128 ] ( 0, 0 ) long -> zero-ref "field V47._upper (fldOffset=0x8)" P-INDEP ;* V129 tmp120 [V129 ] ( 0, 0 ) long -> zero-ref "field V51._lower (fldOffset=0x0)" P-INDEP -; V130 tmp121 [V130,T21] ( 2, 2 ) long -> [rbp-0x20] spill-single-def "field V51._upper (fldOffset=0x8)" P-INDEP +; V130 tmp121 [V130,T21] ( 2, 2 ) long -> rdi "field V51._upper (fldOffset=0x8)" P-INDEP ;* V131 tmp122 [V131 ] ( 0, 0 ) long -> zero-ref "field V56._lower (fldOffset=0x0)" P-INDEP ;* V132 tmp123 [V132 ] ( 0, 0 ) long -> zero-ref "field V56._upper (fldOffset=0x8)" P-INDEP ;* V133 tmp124 [V133 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V58.Item1 (fldOffset=0x0)" P-DEP ;* V134 tmp125 [V134 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V58.Item2 (fldOffset=0x8)" P-DEP ; V135 tmp126 [V135,T11] ( 3, 3 ) long -> rax "field V59.Item1 (fldOffset=0x0)" P-INDEP ; V136 tmp127 [V136,T22] ( 2, 2 ) long -> rdx "field V59.Item2 (fldOffset=0x8)" P-INDEP ;* V137 tmp128 [V137 ] ( 0, 0 ) long -> zero-ref "field V62._lower (fldOffset=0x0)" P-INDEP ;* V138 tmp129 [V138 ] ( 0, 0 ) long -> zero-ref "field V62._upper (fldOffset=0x8)" P-INDEP ;* V139 tmp130 [V139 ] ( 0, 0 ) long -> zero-ref "field V66._lower (fldOffset=0x0)" P-INDEP ; V140 tmp131 [V140,T23] ( 2, 2 ) long -> rdx "field V66._upper (fldOffset=0x8)" P-INDEP ;* V141 tmp132 [V141 ] ( 0, 0 ) long -> zero-ref "field V69._lower (fldOffset=0x0)" P-INDEP ;* V142 tmp133 [V142 ] ( 0, 0 ) long -> zero-ref "field V69._upper (fldOffset=0x8)" P-INDEP ;* V143 tmp134 [V143 ] ( 0, 0 ) long -> zero-ref "field V73._lower (fldOffset=0x0)" P-INDEP ; V144 tmp135 [V144,T24] ( 2, 2 ) long -> rdx "field V73._upper (fldOffset=0x8)" P-INDEP ; -; Lcl frame size = 32 +; Lcl frame size = 0 G_M54025_IG01: push rbp - sub rsp, 32 - lea rbp, [rsp+0x20] - ;; size=10 bbWeight=1 PerfScore 1.75 + mov rbp, rsp + mov rax, rcx + ;; size=7 bbWeight=1 PerfScore 1.50 G_M54025_IG02: - mov qword ptr [rbp-0x08], rdx - mov rax, rdi - mul rdx:rax, rdx - mov qword ptr [rbp-0x10], rax - mov qword ptr [rbp-0x18], rdx - mov rax, rsi - mul rdx:rax, qword ptr [rbp-0x08] - mov r9, qword ptr [rbp-0x18] - add r9, rax - cmp r9, rax - setb al - movzx rax, al - mov r10d, eax - add r10, rdx - mov rax, rdi - mul rdx:rax, rcx - add r9, rax - cmp r9, rax - setb al - movzx rax, al - add rax, rdx - mov qword ptr [rbp-0x20], rax - mov rdx, qword ptr [rbp-0x10] - mov qword ptr [r8], rdx + mulx r9, rcx, rdi + mulx r10, rdx, rsi + add r9, rdx + cmp r9, rdx + setb dl + movzx rdx, dl + mov r11d, edx + add r10, r11 + mov rdx, rdi + mulx rdi, rdx, rax + add r9, rdx + cmp r9, rdx + setb dl + movzx rdx, dl + mov r11d, edx + add rdi, r11 + mov qword ptr [r8], rcx mov qword ptr [r8+0x08], r9 - mov rax, rsi - mul rdx:rax, rcx + mov rdx, rsi + mulx rdx, rax, rax add r10, rax cmp r10, rax setb al movzx rax, al add rdx, rax - mov rax, r10 - add rax, qword ptr [rbp-0x20] + lea rax, [r10+rdi] cmp rax, r10 setb cl movzx rcx, cl add rdx, rcx - ;; size=123 bbWeight=1 PerfScore 30.25 + ;; size=100 bbWeight=1 PerfScore 21.25 G_M54025_IG03: - add rsp, 32 pop rbp ret - ;; size=6 bbWeight=1 PerfScore 1.75 + ;; size=2 bbWeight=1 PerfScore 1.50 -; Total bytes of code 139, prolog size 10, PerfScore 33.75, instruction count 44, allocated bytes for code 139 (MethodHash=0f562cf6) for method System.UInt128:BigMul(System.UInt128,System.UInt128,byref):System.UInt128 (FullOpts) +; Total bytes of code 109, prolog size 4, PerfScore 24.25, instruction count 35, allocated bytes for code 109 (MethodHash=0f562cf6) for method System.UInt128:BigMul(System.UInt128,System.UInt128,byref):System.UInt128 (FullOpts) ; ============================================================ ```
-25 (-6.79 % of base) - System.UInt128:g__DivideSlow|83_0(System.UInt128,System.UInt128):System.ValueTuple`2[ulong,System.UInt128] ```diff ; Assembly listing for method System.UInt128:g__DivideSlow|83_0(System.UInt128,System.UInt128):System.ValueTuple`2[ulong,System.UInt128] (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rbp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 14 single block inlinees; 6 inlinees without PGO data ; Final local variable assignments ; ; V00 RetBuf [V00,T08] ( 6, 6 ) long -> rdi single-def ;* V01 arg0 [V01 ] ( 0, 0 ) struct (16) zero-ref multireg-arg single-def ;* V02 arg1 [V02 ] ( 0, 0 ) struct (16) zero-ref multireg-arg single-def ; V03 loc0 [V03,T12] ( 8, 6.50) long -> r9 ; V04 loc1 [V04,T21] ( 4, 3.50) long -> r10 ; V05 loc2 [V05,T03] ( 7, 15 ) long -> r14 ; V06 loc3 [V06,T20] ( 5, 3.50) long -> r11 ; V07 loc4 [V07,T30] ( 3, 2.50) long -> rbx ; V08 loc5 [V08,T19] ( 5, 4 ) int -> r15 -; V09 loc6 [V09,T04] ( 6, 12 ) long -> [rbp-0x28] +; V09 loc6 [V09,T04] ( 6, 12 ) long -> rax ;* V10 loc7 [V10 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op -; V11 loc8 [V11,T01] ( 7, 19 ) long -> rcx +; V11 loc8 [V11,T01] ( 7, 19 ) long -> r8 ;* V12 loc9 [V12 ] ( 0, 0 ) long -> zero-ref ld-addr-op ;* V13 loc10 [V13 ] ( 0, 0 ) long -> zero-ref ;* V14 loc11 [V14 ] ( 0, 0 ) long -> zero-ref ld-addr-op -; V15 loc12 [V15,T24] ( 3, 3 ) long -> r8 +; V15 loc12 [V15,T24] ( 3, 3 ) long -> rcx ;* V16 loc13 [V16 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V17 loc14 [V17 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V18 loc15 [V18 ] ( 0, 0 ) struct (16) zero-ref ; V19 loc16 [V19,T37] ( 2, 1 ) int -> r11 ;# V20 OutArgs [V20 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ;* V21 tmp1 [V21 ] ( 0, 0 ) struct (16) zero-ref "location for address-of(RValue)" ; V22 tmp2 [V22,T32] ( 3, 2 ) long -> rax ;* V23 tmp3 [V23 ] ( 0, 0 ) struct (32) zero-ref do-not-enreg[SF] ld-addr-op "NewObj constructor temp" ;* V24 tmp4 [V24 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V25 tmp5 [V25 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline return value spill temp" ;* V26 tmp6 [V26 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ; V27 tmp7 [V27,T38] ( 2, 1 ) long -> rax "Inline stloc first use temp" ;* V28 tmp8 [V28 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V29 tmp9 [V29 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V30 tmp10 [V30 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V31 tmp11 [V31 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V32 tmp12 [V32 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V33 tmp13 [V33 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V34 tmp14 [V34 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V35 tmp15 [V35 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V36 tmp16 [V36 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V37 tmp17 [V37 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp" ;* V38 tmp18 [V38 ] ( 0, 0 ) struct (16) zero-ref "Inlining Arg" ;* V39 tmp19 [V39 ] ( 0, 0 ) struct (16) zero-ref "Inlining Arg" ;* V40 tmp20 [V40 ] ( 0, 0 ) struct (16) zero-ref "Inlining Arg" ;* V41 tmp21 [V41 ] ( 0, 0 ) struct (16) zero-ref "Inlining Arg" -; V42 tmp22 [V42,T05] ( 3, 12 ) long -> rdx "Inline stloc first use temp" -; V43 tmp23 [V43,T09] ( 2, 8 ) long -> rax "Inline stloc first use temp" +; V42 tmp22 [V42,T05] ( 3, 12 ) long -> rsi "Inline stloc first use temp" +; V43 tmp23 [V43,T09] ( 2, 8 ) long -> rdx "Inline stloc first use temp" ;* V44 tmp24 [V44 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V45 tmp25 [V45 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V46 tmp26 [V46 ] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp" ;* V47 tmp27 [V47 ] ( 0, 0 ) struct (16) zero-ref "Inlining Arg" ;* V48 tmp28 [V48 ] ( 0, 0 ) struct (16) zero-ref "Inlining Arg" ;* V49 tmp29 [V49 ] ( 0, 0 ) struct (16) zero-ref "Inlining Arg" ;* V50 tmp30 [V50 ] ( 0, 0 ) struct (16) zero-ref "Inlining Arg" -; V51 tmp31 [V51,T23] ( 4, 3 ) long -> rcx "Inline stloc first use temp" -; V52 tmp32 [V52,T33] ( 2, 2 ) long -> rax "Inline stloc first use temp" +; V51 tmp31 [V51,T23] ( 4, 3 ) long -> rsi "Inline stloc first use temp" +; V52 tmp32 [V52,T33] ( 2, 2 ) long -> rdx "Inline stloc first use temp" ;* V53 tmp33 [V53 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V54 tmp34 [V54 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V55 tmp35 [V55 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ; V56 tmp36 [V56,T07] ( 7, 9 ) int -> r15 "Inlining Arg" ;* V57 tmp37 [V57 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V58 tmp38 [V58 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V59 tmp39 [V59 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V60 tmp40 [V60 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V61 tmp41 [V61 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V62 tmp42 [V62,T14] ( 4, 3 ) long -> rsi single-def "field V01._lower (fldOffset=0x0)" P-INDEP ; V63 tmp43 [V63,T15] ( 4, 3 ) long -> rdx single-def "field V01._upper (fldOffset=0x8)" P-INDEP ; V64 tmp44 [V64,T16] ( 4, 3 ) long -> rcx single-def "field V02._lower (fldOffset=0x0)" P-INDEP ; V65 tmp45 [V65,T18] ( 3, 2.50) long -> r8 single-def "field V02._upper (fldOffset=0x8)" P-INDEP ; V66 tmp46 [V66,T17] ( 4, 5 ) long -> rbx "field V10._lower (fldOffset=0x0)" P-INDEP ; V67 tmp47 [V67,T13] ( 4, 6 ) long -> r11 "field V10._upper (fldOffset=0x8)" P-INDEP ; V68 tmp48 [V68,T11] ( 3, 7 ) long -> r10 "field V16._lower (fldOffset=0x0)" P-INDEP ; V69 tmp49 [V69,T06] ( 4, 11 ) long -> r9 "field V16._upper (fldOffset=0x8)" P-INDEP -; V70 tmp50 [V70,T02] ( 7, 18 ) long -> rax "field V17._lower (fldOffset=0x0)" P-INDEP -; V71 tmp51 [V71,T00] ( 8, 20 ) long -> r8 "field V17._upper (fldOffset=0x8)" P-INDEP +; V70 tmp50 [V70,T02] ( 7, 18 ) long -> rdx "field V17._lower (fldOffset=0x0)" P-INDEP +; V71 tmp51 [V71,T00] ( 8, 20 ) long -> rcx "field V17._upper (fldOffset=0x8)" P-INDEP ;* V72 tmp52 [V72 ] ( 0, 0 ) long -> zero-ref "field V18._lower (fldOffset=0x0)" P-INDEP ;* V73 tmp53 [V73 ] ( 0, 0 ) long -> zero-ref "field V18._upper (fldOffset=0x8)" P-INDEP ;* V74 tmp54 [V74 ] ( 0, 0 ) long -> zero-ref "field V21.Item1 (fldOffset=0x0)" P-INDEP ;* V75 tmp55 [V75 ] ( 0, 0 ) long -> zero-ref "field V21.Item2 (fldOffset=0x8)" P-INDEP ;* V76 tmp56 [V76 ] ( 0, 0 ) long -> zero-ref "field V24._lower (fldOffset=0x0)" P-INDEP ;* V77 tmp57 [V77 ] ( 0, 0 ) long -> zero-ref "field V24._upper (fldOffset=0x8)" P-INDEP ; V78 tmp58 [V78,T36] ( 3, 1.50) long -> rax "field V25.Item1 (fldOffset=0x0)" P-INDEP ; V79 tmp59 [V79,T42] ( 1, 0.50) long -> rdx "field V25.Item2 (fldOffset=0x8)" P-INDEP ;* V80 tmp60 [V80 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V26.Item1 (fldOffset=0x0)" P-DEP ;* V81 tmp61 [V81 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V26.Item2 (fldOffset=0x8)" P-DEP ;* V82 tmp62 [V82 ] ( 0, 0 ) long -> zero-ref "field V28.Item1 (fldOffset=0x0)" P-INDEP ;* V83 tmp63 [V83 ] ( 0, 0 ) long -> zero-ref "field V28.Item2 (fldOffset=0x8)" P-INDEP ;* V84 tmp64 [V84 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V31.Item1 (fldOffset=0x0)" P-DEP ;* V85 tmp65 [V85 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V31.Item2 (fldOffset=0x8)" P-DEP -; V86 tmp66 [V86,T34] ( 2, 2 ) long -> [rbp-0x30] spill-single-def "field V32.Item1 (fldOffset=0x0)" P-INDEP -; V87 tmp67 [V87,T25] ( 3, 3 ) long -> [rbp-0x38] spill-single-def "field V32.Item2 (fldOffset=0x8)" P-INDEP +; V86 tmp66 [V86,T34] ( 2, 2 ) long -> rcx "field V32.Item1 (fldOffset=0x0)" P-INDEP +; V87 tmp67 [V87,T25] ( 3, 3 ) long -> rsi "field V32.Item2 (fldOffset=0x8)" P-INDEP ;* V88 tmp68 [V88 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V34.Item1 (fldOffset=0x0)" P-DEP ;* V89 tmp69 [V89 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V34.Item2 (fldOffset=0x8)" P-DEP -; V90 tmp70 [V90,T35] ( 2, 2 ) long -> rax "field V35.Item1 (fldOffset=0x0)" P-INDEP -; V91 tmp71 [V91,T26] ( 3, 3 ) long -> rdx "field V35.Item2 (fldOffset=0x8)" P-INDEP +; V90 tmp70 [V90,T35] ( 2, 2 ) long -> rdx "field V35.Item1 (fldOffset=0x0)" P-INDEP +; V91 tmp71 [V91,T26] ( 3, 3 ) long -> r13 "field V35.Item2 (fldOffset=0x8)" P-INDEP ;* V92 tmp72 [V92 ] ( 0, 0 ) long -> zero-ref "field V38._lower (fldOffset=0x0)" P-INDEP ;* V93 tmp73 [V93 ] ( 0, 0 ) long -> zero-ref "field V38._upper (fldOffset=0x8)" P-INDEP ;* V94 tmp74 [V94 ] ( 0, 0 ) long -> zero-ref "field V39._lower (fldOffset=0x0)" P-INDEP ;* V95 tmp75 [V95 ] ( 0, 0 ) long -> zero-ref "field V39._upper (fldOffset=0x8)" P-INDEP ;* V96 tmp76 [V96 ] ( 0, 0 ) long -> zero-ref "field V40._lower (fldOffset=0x0)" P-INDEP ;* V97 tmp77 [V97 ] ( 0, 0 ) long -> zero-ref "field V40._upper (fldOffset=0x8)" P-INDEP ;* V98 tmp78 [V98 ] ( 0, 0 ) long -> zero-ref "field V41._lower (fldOffset=0x0)" P-INDEP ;* V99 tmp79 [V99 ] ( 0, 0 ) long -> zero-ref "field V41._upper (fldOffset=0x8)" P-INDEP ;* V100 tmp80 [V100 ] ( 0, 0 ) long -> zero-ref "field V44._lower (fldOffset=0x0)" P-INDEP -; V101 tmp81 [V101,T10] ( 2, 8 ) long -> r8 "field V44._upper (fldOffset=0x8)" P-INDEP +; V101 tmp81 [V101,T10] ( 2, 8 ) long -> rcx "field V44._upper (fldOffset=0x8)" P-INDEP ;* V102 tmp82 [V102 ] ( 0, 0 ) long -> zero-ref "field V47._lower (fldOffset=0x0)" P-INDEP ;* V103 tmp83 [V103 ] ( 0, 0 ) long -> zero-ref "field V47._upper (fldOffset=0x8)" P-INDEP ;* V104 tmp84 [V104 ] ( 0, 0 ) long -> zero-ref "field V48._lower (fldOffset=0x0)" P-INDEP ;* V105 tmp85 [V105 ] ( 0, 0 ) long -> zero-ref "field V48._upper (fldOffset=0x8)" P-INDEP ;* V106 tmp86 [V106 ] ( 0, 0 ) long -> zero-ref "field V49._lower (fldOffset=0x0)" P-INDEP ;* V107 tmp87 [V107 ] ( 0, 0 ) long -> zero-ref "field V49._upper (fldOffset=0x8)" P-INDEP ;* V108 tmp88 [V108 ] ( 0, 0 ) long -> zero-ref "field V50._lower (fldOffset=0x0)" P-INDEP ;* V109 tmp89 [V109 ] ( 0, 0 ) long -> zero-ref "field V50._upper (fldOffset=0x8)" P-INDEP ;* V110 tmp90 [V110 ] ( 0, 0 ) long -> zero-ref "field V53._lower (fldOffset=0x0)" P-INDEP ; V111 tmp91 [V111,T22] ( 5, 3 ) long -> r11 "field V53._upper (fldOffset=0x8)" P-INDEP -; V112 tmp92 [V112,T28] ( 4, 2.50) long -> rcx "field V55._lower (fldOffset=0x0)" P-INDEP +; V112 tmp92 [V112,T28] ( 4, 2.50) long -> rsi "field V55._lower (fldOffset=0x0)" P-INDEP ; V113 tmp93 [V113,T29] ( 4, 2.50) long -> r11 "field V55._upper (fldOffset=0x8)" P-INDEP -; V114 tmp94 [V114,T39] ( 2, 1 ) long -> rcx "field V58._lower (fldOffset=0x0)" P-INDEP +; V114 tmp94 [V114,T39] ( 2, 1 ) long -> rsi "field V58._lower (fldOffset=0x0)" P-INDEP ; V115 tmp95 [V115,T40] ( 2, 1 ) long -> r11 "field V58._upper (fldOffset=0x8)" P-INDEP -; V116 tmp96 [V116,T41] ( 2, 1 ) long -> rcx "field V60._lower (fldOffset=0x0)" P-INDEP +; V116 tmp96 [V116,T41] ( 2, 1 ) long -> rsi "field V60._lower (fldOffset=0x0)" P-INDEP ;* V117 tmp97 [V117 ] ( 0, 0 ) long -> zero-ref "field V60._upper (fldOffset=0x8)" P-INDEP ;* V118 tmp98 [V118 ] ( 0, 0 ) long -> zero-ref "V23.[000..008)" ;* V119 tmp99 [V119 ] ( 0, 0 ) long -> zero-ref "V23.[016..024)" ;* V120 tmp100 [V120 ] ( 0, 0 ) long -> zero-ref "V23.[024..032)" ; V121 cse0 [V121,T31] ( 4, 2 ) int -> r11 "CSE #02: conservative" ; V122 cse1 [V122,T27] ( 5, 2.50) int -> rax "CSE #01: conservative" ; -; Lcl frame size = 32 +; Lcl frame size = 0 G_M37024_IG01: push rbp push r15 push r14 push r13 push rbx - sub rsp, 32 - lea rbp, [rsp+0x40] - ;; size=17 bbWeight=1 PerfScore 5.75 + lea rbp, [rsp+0x20] + ;; size=13 bbWeight=1 PerfScore 5.50 G_M37024_IG02: mov r9, r8 mov r10, rcx mov r11, rdx mov rbx, rsi xor r15d, r15d lzcnt r15, r9 test r15d, r15d jg SHORT G_M37024_IG04 ;; size=25 bbWeight=1 PerfScore 4.50 G_M37024_IG03: xor r14d, r14d jmp SHORT G_M37024_IG05 ;; size=5 bbWeight=0.50 PerfScore 1.12 G_M37024_IG04: mov r11d, r15d neg r11d add r11d, 64 mov eax, r15d and eax, 63 shlx r9, r8, rax and r11d, 63 shrx r10, rcx, r11 or r9, r10 shlx r10, rcx, rax shrx r14, rdx, r11 shlx rdx, rdx, rax shrx r11, rsi, r11 or r11, rdx shlx rbx, rsi, rax ;; size=61 bbWeight=0.50 PerfScore 2.75 G_M37024_IG05: cmp r14, r9 jae SHORT G_M37024_IG09 ;; size=5 bbWeight=1 PerfScore 1.25 G_M37024_IG06: test r14, r14 je SHORT G_M37024_IG07 mov rax, r11 mov rdx, r14 div rdx:rax, r9 jmp SHORT G_M37024_IG08 ;; size=16 bbWeight=0.50 PerfScore 32.38 G_M37024_IG07: mov rax, r11 xor edx, edx div rdx:rax, r9 ;; size=8 bbWeight=0.50 PerfScore 30.75 G_M37024_IG08: jmp SHORT G_M37024_IG10 ;; size=2 bbWeight=0.50 PerfScore 1.00 G_M37024_IG09: mov rax, -1 ;; size=10 bbWeight=0.50 PerfScore 0.12 G_M37024_IG10: - mov qword ptr [rbp-0x28], rax - mul rdx:rax, r9 - mov qword ptr [rbp-0x30], rax - mov qword ptr [rbp-0x38], rdx - mov rcx, rdx - mov rsi, qword ptr [rbp-0x28] - mov rax, rsi - mul rdx:rax, r10 - mov r8, rdx - add r8, qword ptr [rbp-0x30] - mov r13, qword ptr [rbp-0x38] - inc r13 - cmp r8, rdx - cmovb rcx, r13 + mov rdx, rax + mulx rsi, rcx, r9 + mov r8, rsi + mov rdx, rax + mulx r13, rdx, r10 + add rcx, r13 + inc rsi + cmp rcx, r13 + cmovb r8, rsi jmp SHORT G_M37024_IG16 - ;; size=51 bbWeight=1 PerfScore 15.75 + ;; size=34 bbWeight=1 PerfScore 10.00 G_M37024_IG11: - cmp r8, r11 + cmp rcx, r11 ja SHORT G_M37024_IG12 jne SHORT G_M37024_IG18 - cmp rax, rbx + cmp rdx, rbx jbe SHORT G_M37024_IG18 ;; size=12 bbWeight=2 PerfScore 7.00 G_M37024_IG12: - dec rsi - cmp r8, r9 + dec rax + cmp rcx, r9 jb SHORT G_M37024_IG14 ;; size=8 bbWeight=4 PerfScore 6.00 G_M37024_IG13: - cmp r8, r9 + cmp rcx, r9 jne SHORT G_M37024_IG15 - cmp rax, r10 + cmp rdx, r10 jae SHORT G_M37024_IG15 ;; size=10 bbWeight=2 PerfScore 5.00 G_M37024_IG14: - dec rcx + dec r8 ;; size=3 bbWeight=2 PerfScore 0.50 G_M37024_IG15: - mov rdx, rax - sub rdx, r10 - cmp rdx, rax - seta al - movzx rax, al - sub r8, r9 - sub r8, rax - mov rax, rdx + mov rsi, rdx + sub rsi, r10 + cmp rsi, rdx + seta dl + movzx rdx, dl + sub rcx, r9 + sub rcx, rdx + mov rdx, rsi ;; size=24 bbWeight=4 PerfScore 9.00 G_M37024_IG16: - cmp rcx, r14 + cmp r8, r14 ja SHORT G_M37024_IG12 ;; size=5 bbWeight=8 PerfScore 10.00 G_M37024_IG17: - cmp rcx, r14 + cmp r8, r14 je SHORT G_M37024_IG11 ;; size=5 bbWeight=4 PerfScore 5.00 G_M37024_IG18: - mov rcx, rbx - sub rcx, rax - cmp rcx, rbx - seta al - movzx rax, al - sub r11, r8 - sub r11, rax + mov rsi, rbx + sub rsi, rdx + cmp rsi, rbx + seta dl + movzx rdx, dl + sub r11, rcx + sub r11, rdx and r15d, 127 test r15b, 64 jne SHORT G_M37024_IG21 ;; size=31 bbWeight=1 PerfScore 3.50 G_M37024_IG19: test r15d, r15d jne SHORT G_M37024_IG20 jmp SHORT G_M37024_IG22 ;; size=7 bbWeight=0.50 PerfScore 1.62 G_M37024_IG20: - shrx rcx, rcx, r15 - mov eax, r15d - neg eax - add eax, 64 - shlx rax, r11, rax - or rcx, rax + shrx rsi, rsi, r15 + mov ecx, r15d + neg ecx + add ecx, 64 + shlx rcx, r11, rcx + or rsi, rcx shrx r11, r11, r15 jmp SHORT G_M37024_IG22 ;; size=28 bbWeight=0.50 PerfScore 2.25 G_M37024_IG21: - shrx rcx, r11, r15 + shrx rsi, r11, r15 xor r11d, r11d ;; size=8 bbWeight=0.50 PerfScore 0.38 G_M37024_IG22: - mov qword ptr [rdi], rsi - mov qword ptr [rdi+0x10], rcx + mov qword ptr [rdi], rax + mov qword ptr [rdi+0x10], rsi mov qword ptr [rdi+0x18], r11 mov rax, rdi ;; size=14 bbWeight=1 PerfScore 3.25 G_M37024_IG23: - add rsp, 32 pop rbx pop r13 pop r14 pop r15 pop rbp ret - ;; size=13 bbWeight=1 PerfScore 3.75 + ;; size=9 bbWeight=1 PerfScore 3.50 -; Total bytes of code 368, prolog size 17, PerfScore 152.62, instruction count 119, allocated bytes for code 368 (MethodHash=2af36f5f) for method System.UInt128:g__DivideSlow|83_0(System.UInt128,System.UInt128):System.ValueTuple`2[ulong,System.UInt128] (FullOpts) +; Total bytes of code 343, prolog size 13, PerfScore 146.38, instruction count 112, allocated bytes for code 343 (MethodHash=2af36f5f) for method System.UInt128:g__DivideSlow|83_0(System.UInt128,System.UInt128):System.ValueTuple`2[ulong,System.UInt128] (FullOpts) ; ============================================================ ```
-23 (-4.89 % of base) - System.Numerics.BigIntegerCalculator:Mul1(System.Span`1[nuint],System.ReadOnlySpan`1[nuint],nuint):nuint ```diff ; Assembly listing for method System.Numerics.BigIntegerCalculator:Mul1(System.Span`1[nuint],System.ReadOnlySpan`1[nuint],nuint):nuint (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rbp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 75 single block inlinees; 10 inlinees without PGO data ; Final local variable assignments ; ;* V00 arg0 [V00 ] ( 0, 0 ) struct (16) zero-ref multireg-arg ld-addr-op single-def ;* V01 arg1 [V01 ] ( 0, 0 ) struct (16) zero-ref multireg-arg ld-addr-op single-def ; V02 arg2 [V02,T01] ( 8, 22 ) long -> r8 single-def -; V03 loc0 [V03,T04] ( 7, 21 ) int -> r9 -; V04 loc1 [V04,T00] ( 25, 61.83) int -> r10 -; V05 loc2 [V05,T06] ( 8, 18 ) long -> [rbp-0x18] +; V03 loc0 [V03,T04] ( 7, 21 ) int -> rax +; V04 loc1 [V04,T00] ( 25, 61.83) int -> r9 +; V05 loc2 [V05,T06] ( 8, 18 ) long -> r10 ;* V06 loc3 [V06 ] ( 0, 0 ) struct (16) zero-ref ;* V07 loc4 [V07 ] ( 0, 0 ) struct (16) zero-ref ;* V08 loc5 [V08 ] ( 0, 0 ) struct (16) zero-ref ;* V09 loc6 [V09 ] ( 0, 0 ) struct (16) zero-ref ;* V10 loc7 [V10 ] ( 0, 0 ) struct (16) zero-ref ;# V11 OutArgs [V11 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ;* V12 tmp1 [V12 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V13 tmp2 [V13 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V14 tmp3 [V14 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V15 tmp4 [V15 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V16 tmp5 [V16 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V17 tmp6 [V17 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V18 tmp7 [V18 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V19 tmp8 [V19 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V20 tmp9 [V20 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V21 tmp10 [V21 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V22 tmp11 [V22 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V23 tmp12 [V23 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V24 tmp13 [V24 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V25 tmp14 [V25 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V26 tmp15 [V26 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V27 tmp16 [V27 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V28 tmp17 [V28 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V29 tmp18 [V29 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V30 tmp19 [V30 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V31 tmp20 [V31 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V32 tmp21 [V32 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V33 tmp22 [V33 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V34 tmp23 [V34 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V35 tmp24 [V35 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V36 tmp25 [V36 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V37 tmp26 [V37 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V38 tmp27 [V38 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V39 tmp28 [V39 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V40 tmp29 [V40 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V41 tmp30 [V41 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V42 tmp31 [V42 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V43 tmp32 [V43 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V44 tmp33 [V44 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V45 tmp34 [V45 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V46 tmp35 [V46 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V47 tmp36 [V47 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V48 tmp37 [V48 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V49 tmp38 [V49 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V50 tmp39 [V50 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V51 tmp40 [V51 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V52 tmp41 [V52 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V53 tmp42 [V53 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V54 tmp43 [V54 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" -; V55 tmp44 [V55,T12] ( 3, 12 ) long -> r11 "Inline stloc first use temp" -; V56 tmp45 [V56,T28] ( 2, 8 ) long -> rax "Inline stloc first use temp" +; V55 tmp44 [V55,T12] ( 3, 12 ) long -> r10 "Inline stloc first use temp" +; V56 tmp45 [V56,T28] ( 2, 8 ) long -> rdx "Inline stloc first use temp" ;* V57 tmp46 [V57 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V58 tmp47 [V58 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V59 tmp48 [V59 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V60 tmp49 [V60 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V61 tmp50 [V61 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V62 tmp51 [V62 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V63 tmp52 [V63 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V64 tmp53 [V64 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V65 tmp54 [V65 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V66 tmp55 [V66 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V67 tmp56 [V67 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V68 tmp57 [V68 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V69 tmp58 [V69 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V70 tmp59 [V70 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V71 tmp60 [V71 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V72 tmp61 [V72 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V73 tmp62 [V73 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V74 tmp63 [V74 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V75 tmp64 [V75 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V76 tmp65 [V76 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V77 tmp66 [V77 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V78 tmp67 [V78 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V79 tmp68 [V79 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V80 tmp69 [V80 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" -; V81 tmp70 [V81,T13] ( 3, 12 ) long -> r15 "Inline stloc first use temp" -; V82 tmp71 [V82,T29] ( 2, 8 ) long -> rax "Inline stloc first use temp" +; V81 tmp70 [V81,T13] ( 3, 12 ) long -> r11 "Inline stloc first use temp" +; V82 tmp71 [V82,T29] ( 2, 8 ) long -> rdx "Inline stloc first use temp" ;* V83 tmp72 [V83 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V84 tmp73 [V84 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V85 tmp74 [V85 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V86 tmp75 [V86 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V87 tmp76 [V87 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V88 tmp77 [V88 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V89 tmp78 [V89 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V90 tmp79 [V90 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V91 tmp80 [V91 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V92 tmp81 [V92 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V93 tmp82 [V93 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V94 tmp83 [V94 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V95 tmp84 [V95 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V96 tmp85 [V96 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V97 tmp86 [V97 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V98 tmp87 [V98 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V99 tmp88 [V99 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V100 tmp89 [V100 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V101 tmp90 [V101 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V102 tmp91 [V102 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V103 tmp92 [V103 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V104 tmp93 [V104 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V105 tmp94 [V105 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V106 tmp95 [V106 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V107 tmp96 [V107,T14] ( 3, 12 ) long -> r15 "Inline stloc first use temp" -; V108 tmp97 [V108,T30] ( 2, 8 ) long -> rax "Inline stloc first use temp" +; V108 tmp97 [V108,T30] ( 2, 8 ) long -> rdx "Inline stloc first use temp" ;* V109 tmp98 [V109 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V110 tmp99 [V110 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V111 tmp100 [V111 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V112 tmp101 [V112 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V113 tmp102 [V113 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V114 tmp103 [V114 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V115 tmp104 [V115 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V116 tmp105 [V116 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V117 tmp106 [V117 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V118 tmp107 [V118 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V119 tmp108 [V119 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V120 tmp109 [V120 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V121 tmp110 [V121 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V122 tmp111 [V122 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V123 tmp112 [V123 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V124 tmp113 [V124 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V125 tmp114 [V125 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V126 tmp115 [V126 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V127 tmp116 [V127 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V128 tmp117 [V128 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V129 tmp118 [V129 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V130 tmp119 [V130 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V131 tmp120 [V131 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V132 tmp121 [V132 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" -; V133 tmp122 [V133,T15] ( 3, 12 ) long -> r15 "Inline stloc first use temp" -; V134 tmp123 [V134,T31] ( 2, 8 ) long -> rax "Inline stloc first use temp" +; V133 tmp122 [V133,T15] ( 3, 12 ) long -> rbx "Inline stloc first use temp" +; V134 tmp123 [V134,T31] ( 2, 8 ) long -> rdx "Inline stloc first use temp" ;* V135 tmp124 [V135 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V136 tmp125 [V136 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V137 tmp126 [V137 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V138 tmp127 [V138 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V139 tmp128 [V139 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V140 tmp129 [V140 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V141 tmp130 [V141 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V142 tmp131 [V142 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V143 tmp132 [V143 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V144 tmp133 [V144 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V145 tmp134 [V145 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V146 tmp135 [V146 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V147 tmp136 [V147 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V148 tmp137 [V148 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V149 tmp138 [V149 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V150 tmp139 [V150 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V151 tmp140 [V151 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V152 tmp141 [V152 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V153 tmp142 [V153 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V154 tmp143 [V154 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V155 tmp144 [V155 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V156 tmp145 [V156 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ; V157 tmp146 [V157,T10] ( 6, 12 ) long -> registers "Inline stloc first use temp" ; V158 tmp147 [V158,T24] ( 4, 8 ) long -> registers "Inline stloc first use temp" ;* V159 tmp148 [V159 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V160 tmp149 [V160 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V161 tmp150 [V161 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V162 tmp151 [V162 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V163 tmp152 [V163 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V164 tmp153 [V164 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V165 tmp154 [V165 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V166 tmp155 [V166 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V167 tmp156 [V167 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V168 tmp157 [V168,T02] ( 7, 21 ) byref -> rdi single-def "field V00._reference (fldOffset=0x0)" P-INDEP ; V169 tmp158 [V169,T05] ( 7, 17.29) int -> rsi single-def "field V00._length (fldOffset=0x8)" P-INDEP -; V170 tmp159 [V170,T03] ( 7, 21 ) byref -> [rbp-0x38] single-def "field V01._reference (fldOffset=0x0)" P-INDEP +; V170 tmp159 [V170,T03] ( 7, 21 ) byref -> [rbp-0x18] single-def "field V01._reference (fldOffset=0x0)" P-INDEP ; V171 tmp160 [V171,T23] ( 7, 7.79) int -> rcx single-def "field V01._length (fldOffset=0x8)" P-INDEP ;* V172 tmp161 [V172 ] ( 0, 0 ) long -> zero-ref "field V06._lower (fldOffset=0x0)" P-INDEP ;* V173 tmp162 [V173 ] ( 0, 0 ) long -> zero-ref "field V06._upper (fldOffset=0x8)" P-INDEP ;* V174 tmp163 [V174 ] ( 0, 0 ) long -> zero-ref "field V07._lower (fldOffset=0x0)" P-INDEP ;* V175 tmp164 [V175 ] ( 0, 0 ) long -> zero-ref "field V07._upper (fldOffset=0x8)" P-INDEP ;* V176 tmp165 [V176 ] ( 0, 0 ) long -> zero-ref "field V08._lower (fldOffset=0x0)" P-INDEP ;* V177 tmp166 [V177 ] ( 0, 0 ) long -> zero-ref "field V08._upper (fldOffset=0x8)" P-INDEP ;* V178 tmp167 [V178 ] ( 0, 0 ) long -> zero-ref "field V09._lower (fldOffset=0x0)" P-INDEP ;* V179 tmp168 [V179 ] ( 0, 0 ) long -> zero-ref "field V09._upper (fldOffset=0x8)" P-INDEP ;* V180 tmp169 [V180 ] ( 0, 0 ) long -> zero-ref "field V10._lower (fldOffset=0x0)" P-INDEP ;* V181 tmp170 [V181 ] ( 0, 0 ) long -> zero-ref "field V10._upper (fldOffset=0x8)" P-INDEP ;* V182 tmp171 [V182 ] ( 0, 0 ) long -> zero-ref "field V12._lower (fldOffset=0x0)" P-INDEP ;* V183 tmp172 [V183 ] ( 0, 0 ) long -> zero-ref "field V12._upper (fldOffset=0x8)" P-INDEP ;* V184 tmp173 [V184 ] ( 0, 0 ) long -> zero-ref "field V13._lower (fldOffset=0x0)" P-INDEP ;* V185 tmp174 [V185 ] ( 0, 0 ) long -> zero-ref "field V13._upper (fldOffset=0x8)" P-INDEP ;* V186 tmp175 [V186 ] ( 0, 0 ) long -> zero-ref "field V14._lower (fldOffset=0x0)" P-INDEP ;* V187 tmp176 [V187 ] ( 0, 0 ) long -> zero-ref "field V14._upper (fldOffset=0x8)" P-INDEP ;* V188 tmp177 [V188 ] ( 0, 0 ) long -> zero-ref "field V15._lower (fldOffset=0x0)" P-INDEP ;* V189 tmp178 [V189 ] ( 0, 0 ) long -> zero-ref "field V15._upper (fldOffset=0x8)" P-INDEP ;* V190 tmp179 [V190 ] ( 0, 0 ) long -> zero-ref "field V17._lower (fldOffset=0x0)" P-INDEP ;* V191 tmp180 [V191 ] ( 0, 0 ) long -> zero-ref "field V17._upper (fldOffset=0x8)" P-INDEP ;* V192 tmp181 [V192 ] ( 0, 0 ) long -> zero-ref "field V18._lower (fldOffset=0x0)" P-INDEP ;* V193 tmp182 [V193 ] ( 0, 0 ) long -> zero-ref "field V18._upper (fldOffset=0x8)" P-INDEP ;* V194 tmp183 [V194 ] ( 0, 0 ) long -> zero-ref "field V19._lower (fldOffset=0x0)" P-INDEP ;* V195 tmp184 [V195 ] ( 0, 0 ) long -> zero-ref "field V19._upper (fldOffset=0x8)" P-INDEP ;* V196 tmp185 [V196 ] ( 0, 0 ) long -> zero-ref "field V20._lower (fldOffset=0x0)" P-INDEP ;* V197 tmp186 [V197 ] ( 0, 0 ) long -> zero-ref "field V20._upper (fldOffset=0x8)" P-INDEP ;* V198 tmp187 [V198 ] ( 0, 0 ) long -> zero-ref "field V21._lower (fldOffset=0x0)" P-INDEP ;* V199 tmp188 [V199 ] ( 0, 0 ) long -> zero-ref "field V21._upper (fldOffset=0x8)" P-INDEP ;* V200 tmp189 [V200 ] ( 0, 0 ) long -> zero-ref "field V23._lower (fldOffset=0x0)" P-INDEP ;* V201 tmp190 [V201 ] ( 0, 0 ) long -> zero-ref "field V23._upper (fldOffset=0x8)" P-INDEP ;* V202 tmp191 [V202 ] ( 0, 0 ) long -> zero-ref "field V24._lower (fldOffset=0x0)" P-INDEP ;* V203 tmp192 [V203 ] ( 0, 0 ) long -> zero-ref "field V24._upper (fldOffset=0x8)" P-INDEP ;* V204 tmp193 [V204 ] ( 0, 0 ) long -> zero-ref "field V25._lower (fldOffset=0x0)" P-INDEP ;* V205 tmp194 [V205 ] ( 0, 0 ) long -> zero-ref "field V25._upper (fldOffset=0x8)" P-INDEP ;* V206 tmp195 [V206 ] ( 0, 0 ) long -> zero-ref "field V26._lower (fldOffset=0x0)" P-INDEP ;* V207 tmp196 [V207 ] ( 0, 0 ) long -> zero-ref "field V26._upper (fldOffset=0x8)" P-INDEP ;* V208 tmp197 [V208 ] ( 0, 0 ) long -> zero-ref "field V27._lower (fldOffset=0x0)" P-INDEP ;* V209 tmp198 [V209 ] ( 0, 0 ) long -> zero-ref "field V27._upper (fldOffset=0x8)" P-INDEP ;* V210 tmp199 [V210 ] ( 0, 0 ) long -> zero-ref "field V29._lower (fldOffset=0x0)" P-INDEP ;* V211 tmp200 [V211 ] ( 0, 0 ) long -> zero-ref "field V29._upper (fldOffset=0x8)" P-INDEP ;* V212 tmp201 [V212 ] ( 0, 0 ) long -> zero-ref "field V30._lower (fldOffset=0x0)" P-INDEP ;* V213 tmp202 [V213 ] ( 0, 0 ) long -> zero-ref "field V30._upper (fldOffset=0x8)" P-INDEP ;* V214 tmp203 [V214 ] ( 0, 0 ) long -> zero-ref "field V31._lower (fldOffset=0x0)" P-INDEP ;* V215 tmp204 [V215 ] ( 0, 0 ) long -> zero-ref "field V31._upper (fldOffset=0x8)" P-INDEP ;* V216 tmp205 [V216 ] ( 0, 0 ) long -> zero-ref "field V32._lower (fldOffset=0x0)" P-INDEP ;* V217 tmp206 [V217 ] ( 0, 0 ) long -> zero-ref "field V32._upper (fldOffset=0x8)" P-INDEP ;* V218 tmp207 [V218 ] ( 0, 0 ) long -> zero-ref "field V33._lower (fldOffset=0x0)" P-INDEP ;* V219 tmp208 [V219 ] ( 0, 0 ) long -> zero-ref "field V33._upper (fldOffset=0x8)" P-INDEP ;* V220 tmp209 [V220 ] ( 0, 0 ) long -> zero-ref "field V35._lower (fldOffset=0x0)" P-INDEP ;* V221 tmp210 [V221 ] ( 0, 0 ) long -> zero-ref "field V35._upper (fldOffset=0x8)" P-INDEP ;* V222 tmp211 [V222 ] ( 0, 0 ) long -> zero-ref "field V36._lower (fldOffset=0x0)" P-INDEP ;* V223 tmp212 [V223 ] ( 0, 0 ) long -> zero-ref "field V36._upper (fldOffset=0x8)" P-INDEP ;* V224 tmp213 [V224 ] ( 0, 0 ) long -> zero-ref "field V37._lower (fldOffset=0x0)" P-INDEP ;* V225 tmp214 [V225 ] ( 0, 0 ) long -> zero-ref "field V37._upper (fldOffset=0x8)" P-INDEP ;* V226 tmp215 [V226 ] ( 0, 0 ) long -> zero-ref "field V38._lower (fldOffset=0x0)" P-INDEP ;* V227 tmp216 [V227 ] ( 0, 0 ) long -> zero-ref "field V38._upper (fldOffset=0x8)" P-INDEP ;* V228 tmp217 [V228 ] ( 0, 0 ) long -> zero-ref "field V39._lower (fldOffset=0x0)" P-INDEP ;* V229 tmp218 [V229 ] ( 0, 0 ) long -> zero-ref "field V39._upper (fldOffset=0x8)" P-INDEP ;* V230 tmp219 [V230 ] ( 0, 0 ) long -> zero-ref "field V41._lower (fldOffset=0x0)" P-INDEP ;* V231 tmp220 [V231 ] ( 0, 0 ) long -> zero-ref "field V41._upper (fldOffset=0x8)" P-INDEP ; V232 tmp221 [V232,T32] ( 2, 8 ) long -> r11 "field V43._lower (fldOffset=0x0)" P-INDEP ;* V233 tmp222 [V233 ] ( 0, 0 ) long -> zero-ref "field V43._upper (fldOffset=0x8)" P-INDEP ;* V234 tmp223 [V234 ] ( 0, 0 ) long -> zero-ref "field V44._lower (fldOffset=0x0)" P-INDEP ;* V235 tmp224 [V235 ] ( 0, 0 ) long -> zero-ref "field V44._upper (fldOffset=0x8)" P-INDEP ;* V236 tmp225 [V236 ] ( 0, 0 ) long -> zero-ref "field V46._lower (fldOffset=0x0)" P-INDEP ;* V237 tmp226 [V237 ] ( 0, 0 ) long -> zero-ref "field V46._upper (fldOffset=0x8)" P-INDEP ;* V238 tmp227 [V238 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V50.Item1 (fldOffset=0x0)" P-DEP ;* V239 tmp228 [V239 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V50.Item2 (fldOffset=0x8)" P-DEP -; V240 tmp229 [V240,T16] ( 3, 12 ) long -> rax "field V51.Item1 (fldOffset=0x0)" P-INDEP -; V241 tmp230 [V241,T33] ( 2, 8 ) long -> rdx "field V51.Item2 (fldOffset=0x8)" P-INDEP +; V240 tmp229 [V240,T16] ( 3, 12 ) long -> rdx "field V51.Item1 (fldOffset=0x0)" P-INDEP +; V241 tmp230 [V241,T33] ( 2, 8 ) long -> r11 "field V51.Item2 (fldOffset=0x8)" P-INDEP ;* V242 tmp231 [V242 ] ( 0, 0 ) long -> zero-ref "field V54._lower (fldOffset=0x0)" P-INDEP ;* V243 tmp232 [V243 ] ( 0, 0 ) long -> zero-ref "field V54._upper (fldOffset=0x8)" P-INDEP ;* V244 tmp233 [V244 ] ( 0, 0 ) long -> zero-ref "field V57._lower (fldOffset=0x0)" P-INDEP -; V245 tmp234 [V245,T34] ( 2, 8 ) long -> [rbp-0x20] spill-single-def "field V57._upper (fldOffset=0x8)" P-INDEP +; V245 tmp234 [V245,T34] ( 2, 8 ) long -> r11 "field V57._upper (fldOffset=0x8)" P-INDEP ; V246 tmp235 [V246,T35] ( 2, 8 ) long -> r15 "field V60._lower (fldOffset=0x0)" P-INDEP ;* V247 tmp236 [V247 ] ( 0, 0 ) long -> zero-ref "field V60._upper (fldOffset=0x8)" P-INDEP ;* V248 tmp237 [V248 ] ( 0, 0 ) long -> zero-ref "field V61._lower (fldOffset=0x0)" P-INDEP ;* V249 tmp238 [V249 ] ( 0, 0 ) long -> zero-ref "field V61._upper (fldOffset=0x8)" P-INDEP ;* V250 tmp239 [V250 ] ( 0, 0 ) long -> zero-ref "field V63._lower (fldOffset=0x0)" P-INDEP ;* V251 tmp240 [V251 ] ( 0, 0 ) long -> zero-ref "field V63._upper (fldOffset=0x8)" P-INDEP ;* V252 tmp241 [V252 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V67.Item1 (fldOffset=0x0)" P-DEP ;* V253 tmp242 [V253 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V67.Item2 (fldOffset=0x8)" P-DEP -; V254 tmp243 [V254,T17] ( 3, 12 ) long -> rax "field V68.Item1 (fldOffset=0x0)" P-INDEP -; V255 tmp244 [V255,T36] ( 2, 8 ) long -> rdx "field V68.Item2 (fldOffset=0x8)" P-INDEP +; V254 tmp243 [V254,T17] ( 3, 12 ) long -> rdx "field V68.Item1 (fldOffset=0x0)" P-INDEP +; V255 tmp244 [V255,T36] ( 2, 8 ) long -> r15 "field V68.Item2 (fldOffset=0x8)" P-INDEP ;* V256 tmp245 [V256 ] ( 0, 0 ) long -> zero-ref "field V71._lower (fldOffset=0x0)" P-INDEP ;* V257 tmp246 [V257 ] ( 0, 0 ) long -> zero-ref "field V71._upper (fldOffset=0x8)" P-INDEP ;* V258 tmp247 [V258 ] ( 0, 0 ) long -> zero-ref "field V74._lower (fldOffset=0x0)" P-INDEP ;* V259 tmp248 [V259 ] ( 0, 0 ) long -> zero-ref "field V74._upper (fldOffset=0x8)" P-INDEP ;* V260 tmp249 [V260 ] ( 0, 0 ) long -> zero-ref "field V76._lower (fldOffset=0x0)" P-INDEP ;* V261 tmp250 [V261 ] ( 0, 0 ) long -> zero-ref "field V76._upper (fldOffset=0x8)" P-INDEP ;* V262 tmp251 [V262 ] ( 0, 0 ) long -> zero-ref "field V79._lower (fldOffset=0x0)" P-INDEP ;* V263 tmp252 [V263 ] ( 0, 0 ) long -> zero-ref "field V79._upper (fldOffset=0x8)" P-INDEP ;* V264 tmp253 [V264 ] ( 0, 0 ) long -> zero-ref "field V83._lower (fldOffset=0x0)" P-INDEP -; V265 tmp254 [V265,T37] ( 2, 8 ) long -> [rbp-0x28] spill-single-def "field V83._upper (fldOffset=0x8)" P-INDEP -; V266 tmp255 [V266,T38] ( 2, 8 ) long -> r15 "field V86._lower (fldOffset=0x0)" P-INDEP +; V265 tmp254 [V265,T37] ( 2, 8 ) long -> r15 "field V83._upper (fldOffset=0x8)" P-INDEP +; V266 tmp255 [V266,T38] ( 2, 8 ) long -> rbx "field V86._lower (fldOffset=0x0)" P-INDEP ;* V267 tmp256 [V267 ] ( 0, 0 ) long -> zero-ref "field V86._upper (fldOffset=0x8)" P-INDEP ;* V268 tmp257 [V268 ] ( 0, 0 ) long -> zero-ref "field V87._lower (fldOffset=0x0)" P-INDEP ;* V269 tmp258 [V269 ] ( 0, 0 ) long -> zero-ref "field V87._upper (fldOffset=0x8)" P-INDEP ;* V270 tmp259 [V270 ] ( 0, 0 ) long -> zero-ref "field V89._lower (fldOffset=0x0)" P-INDEP ;* V271 tmp260 [V271 ] ( 0, 0 ) long -> zero-ref "field V89._upper (fldOffset=0x8)" P-INDEP ;* V272 tmp261 [V272 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V93.Item1 (fldOffset=0x0)" P-DEP ;* V273 tmp262 [V273 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V93.Item2 (fldOffset=0x8)" P-DEP -; V274 tmp263 [V274,T18] ( 3, 12 ) long -> rax "field V94.Item1 (fldOffset=0x0)" P-INDEP -; V275 tmp264 [V275,T39] ( 2, 8 ) long -> rdx "field V94.Item2 (fldOffset=0x8)" P-INDEP +; V274 tmp263 [V274,T18] ( 3, 12 ) long -> rdx "field V94.Item1 (fldOffset=0x0)" P-INDEP +; V275 tmp264 [V275,T39] ( 2, 8 ) long -> rbx "field V94.Item2 (fldOffset=0x8)" P-INDEP ;* V276 tmp265 [V276 ] ( 0, 0 ) long -> zero-ref "field V97._lower (fldOffset=0x0)" P-INDEP ;* V277 tmp266 [V277 ] ( 0, 0 ) long -> zero-ref "field V97._upper (fldOffset=0x8)" P-INDEP ;* V278 tmp267 [V278 ] ( 0, 0 ) long -> zero-ref "field V100._lower (fldOffset=0x0)" P-INDEP ;* V279 tmp268 [V279 ] ( 0, 0 ) long -> zero-ref "field V100._upper (fldOffset=0x8)" P-INDEP ;* V280 tmp269 [V280 ] ( 0, 0 ) long -> zero-ref "field V102._lower (fldOffset=0x0)" P-INDEP ;* V281 tmp270 [V281 ] ( 0, 0 ) long -> zero-ref "field V102._upper (fldOffset=0x8)" P-INDEP ;* V282 tmp271 [V282 ] ( 0, 0 ) long -> zero-ref "field V105._lower (fldOffset=0x0)" P-INDEP ;* V283 tmp272 [V283 ] ( 0, 0 ) long -> zero-ref "field V105._upper (fldOffset=0x8)" P-INDEP ;* V284 tmp273 [V284 ] ( 0, 0 ) long -> zero-ref "field V109._lower (fldOffset=0x0)" P-INDEP -; V285 tmp274 [V285,T40] ( 2, 8 ) long -> [rbp-0x30] spill-single-def "field V109._upper (fldOffset=0x8)" P-INDEP +; V285 tmp274 [V285,T40] ( 2, 8 ) long -> rbx "field V109._upper (fldOffset=0x8)" P-INDEP ; V286 tmp275 [V286,T41] ( 2, 8 ) long -> r15 "field V112._lower (fldOffset=0x0)" P-INDEP ;* V287 tmp276 [V287 ] ( 0, 0 ) long -> zero-ref "field V112._upper (fldOffset=0x8)" P-INDEP ;* V288 tmp277 [V288 ] ( 0, 0 ) long -> zero-ref "field V113._lower (fldOffset=0x0)" P-INDEP ;* V289 tmp278 [V289 ] ( 0, 0 ) long -> zero-ref "field V113._upper (fldOffset=0x8)" P-INDEP ;* V290 tmp279 [V290 ] ( 0, 0 ) long -> zero-ref "field V115._lower (fldOffset=0x0)" P-INDEP ;* V291 tmp280 [V291 ] ( 0, 0 ) long -> zero-ref "field V115._upper (fldOffset=0x8)" P-INDEP ;* V292 tmp281 [V292 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V119.Item1 (fldOffset=0x0)" P-DEP ;* V293 tmp282 [V293 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V119.Item2 (fldOffset=0x8)" P-DEP -; V294 tmp283 [V294,T19] ( 3, 12 ) long -> rax "field V120.Item1 (fldOffset=0x0)" P-INDEP -; V295 tmp284 [V295,T42] ( 2, 8 ) long -> rdx "field V120.Item2 (fldOffset=0x8)" P-INDEP +; V294 tmp283 [V294,T19] ( 3, 12 ) long -> rdx "field V120.Item1 (fldOffset=0x0)" P-INDEP +; V295 tmp284 [V295,T42] ( 2, 8 ) long -> r15 "field V120.Item2 (fldOffset=0x8)" P-INDEP ;* V296 tmp285 [V296 ] ( 0, 0 ) long -> zero-ref "field V123._lower (fldOffset=0x0)" P-INDEP ;* V297 tmp286 [V297 ] ( 0, 0 ) long -> zero-ref "field V123._upper (fldOffset=0x8)" P-INDEP ;* V298 tmp287 [V298 ] ( 0, 0 ) long -> zero-ref "field V126._lower (fldOffset=0x0)" P-INDEP ;* V299 tmp288 [V299 ] ( 0, 0 ) long -> zero-ref "field V126._upper (fldOffset=0x8)" P-INDEP ;* V300 tmp289 [V300 ] ( 0, 0 ) long -> zero-ref "field V128._lower (fldOffset=0x0)" P-INDEP ;* V301 tmp290 [V301 ] ( 0, 0 ) long -> zero-ref "field V128._upper (fldOffset=0x8)" P-INDEP ;* V302 tmp291 [V302 ] ( 0, 0 ) long -> zero-ref "field V131._lower (fldOffset=0x0)" P-INDEP ;* V303 tmp292 [V303 ] ( 0, 0 ) long -> zero-ref "field V131._upper (fldOffset=0x8)" P-INDEP ;* V304 tmp293 [V304 ] ( 0, 0 ) long -> zero-ref "field V135._lower (fldOffset=0x0)" P-INDEP -; V305 tmp294 [V305,T43] ( 2, 8 ) long -> rax "field V135._upper (fldOffset=0x8)" P-INDEP +; V305 tmp294 [V305,T43] ( 2, 8 ) long -> rdx "field V135._upper (fldOffset=0x8)" P-INDEP ;* V306 tmp295 [V306 ] ( 0, 0 ) long -> zero-ref "field V137._lower (fldOffset=0x0)" P-INDEP ;* V307 tmp296 [V307 ] ( 0, 0 ) long -> zero-ref "field V137._upper (fldOffset=0x8)" P-INDEP ;* V308 tmp297 [V308 ] ( 0, 0 ) long -> zero-ref "field V140._lower (fldOffset=0x0)" P-INDEP ;* V309 tmp298 [V309 ] ( 0, 0 ) long -> zero-ref "field V140._upper (fldOffset=0x8)" P-INDEP ;* V310 tmp299 [V310 ] ( 0, 0 ) long -> zero-ref "field V142._lower (fldOffset=0x0)" P-INDEP ;* V311 tmp300 [V311 ] ( 0, 0 ) long -> zero-ref "field V142._upper (fldOffset=0x8)" P-INDEP -; V312 tmp301 [V312,T25] ( 4, 8 ) long -> registers "field V145._lower (fldOffset=0x0)" P-INDEP +; V312 tmp301 [V312,T25] ( 4, 8 ) long -> rdx "field V145._lower (fldOffset=0x0)" P-INDEP ;* V313 tmp302 [V313 ] ( 0, 0 ) long -> zero-ref "field V145._upper (fldOffset=0x8)" P-INDEP ;* V314 tmp303 [V314 ] ( 0, 0 ) long -> zero-ref "field V146._lower (fldOffset=0x0)" P-INDEP ;* V315 tmp304 [V315 ] ( 0, 0 ) long -> zero-ref "field V146._upper (fldOffset=0x8)" P-INDEP ;* V316 tmp305 [V316 ] ( 0, 0 ) long -> zero-ref "field V148._lower (fldOffset=0x0)" P-INDEP ;* V317 tmp306 [V317 ] ( 0, 0 ) long -> zero-ref "field V148._upper (fldOffset=0x8)" P-INDEP ;* V318 tmp307 [V318 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V152.Item1 (fldOffset=0x0)" P-DEP ;* V319 tmp308 [V319 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V152.Item2 (fldOffset=0x8)" P-DEP -; V320 tmp309 [V320,T11] ( 6, 12 ) long -> rax "field V153.Item1 (fldOffset=0x0)" P-INDEP -; V321 tmp310 [V321,T26] ( 4, 8 ) long -> rdx "field V153.Item2 (fldOffset=0x8)" P-INDEP +; V320 tmp309 [V320,T11] ( 6, 12 ) long -> registers "field V153.Item1 (fldOffset=0x0)" P-INDEP +; V321 tmp310 [V321,T26] ( 4, 8 ) long -> registers "field V153.Item2 (fldOffset=0x8)" P-INDEP ;* V322 tmp311 [V322 ] ( 0, 0 ) long -> zero-ref "field V156._lower (fldOffset=0x0)" P-INDEP ;* V323 tmp312 [V323 ] ( 0, 0 ) long -> zero-ref "field V156._upper (fldOffset=0x8)" P-INDEP ;* V324 tmp313 [V324 ] ( 0, 0 ) long -> zero-ref "field V159._lower (fldOffset=0x0)" P-INDEP ; V325 tmp314 [V325,T27] ( 4, 8 ) long -> registers "field V159._upper (fldOffset=0x8)" P-INDEP ;* V326 tmp315 [V326 ] ( 0, 0 ) long -> zero-ref "field V161._lower (fldOffset=0x0)" P-INDEP ;* V327 tmp316 [V327 ] ( 0, 0 ) long -> zero-ref "field V161._upper (fldOffset=0x8)" P-INDEP ;* V328 tmp317 [V328 ] ( 0, 0 ) long -> zero-ref "field V164._lower (fldOffset=0x0)" P-INDEP ;* V329 tmp318 [V329 ] ( 0, 0 ) long -> zero-ref "field V164._upper (fldOffset=0x8)" P-INDEP ;* V330 tmp319 [V330 ] ( 0, 0 ) long -> zero-ref "field V166._lower (fldOffset=0x0)" P-INDEP ;* V331 tmp320 [V331 ] ( 0, 0 ) long -> zero-ref "field V166._upper (fldOffset=0x8)" P-INDEP ; V332 cse0 [V332,T20] ( 3, 12 ) long -> rbx "CSE #03: moderate" -; V333 cse1 [V333,T21] ( 3, 12 ) long -> rbx "CSE #05: moderate" -; V334 cse2 [V334,T22] ( 3, 12 ) long -> rbx "CSE #07: moderate" -; V335 cse3 [V335,T07] ( 4, 16 ) int -> r11 "CSE #02: moderate" -; V336 cse4 [V336,T08] ( 4, 16 ) int -> r11 "CSE #04: moderate" -; V337 cse5 [V337,T09] ( 4, 16 ) int -> r11 "CSE #06: moderate" +; V333 cse1 [V333,T21] ( 3, 12 ) long -> r11 "CSE #05: moderate" +; V334 cse2 [V334,T22] ( 3, 12 ) long -> r11 "CSE #07: moderate" +; V335 cse3 [V335,T07] ( 4, 16 ) int -> r10 "CSE #02: moderate" +; V336 cse4 [V336,T08] ( 4, 16 ) int -> r10 "CSE #04: moderate" +; V337 cse5 [V337,T09] ( 4, 16 ) int -> r10 "CSE #06: moderate" ; -; Lcl frame size = 48 +; Lcl frame size = 16 G_M54707_IG01: push rbp push r15 push rbx - sub rsp, 48 - lea rbp, [rsp+0x40] + sub rsp, 16 + lea rbp, [rsp+0x20] ;; size=13 bbWeight=1 PerfScore 3.75 G_M54707_IG02: - mov r9d, ecx + mov eax, ecx + xor r9d, r9d xor r10d, r10d - xor eax, eax - mov qword ptr [rbp-0x18], rax cmp ecx, 3 jg SHORT G_M54707_IG05 - ;; size=17 bbWeight=1 PerfScore 3.00 + ;; size=13 bbWeight=1 PerfScore 2.00 G_M54707_IG03: - mov bword ptr [rbp-0x38], rdx - mov r11, qword ptr [rbp-0x18] + mov bword ptr [rbp-0x18], rdx jmp G_M54707_IG07 align [0 bytes for IG09] - ;; size=13 bbWeight=0.50 PerfScore 2.00 + ;; size=9 bbWeight=0.50 PerfScore 1.50 G_M54707_IG04: - mov qword ptr [rbp-0x18], r11 - mov rdx, bword ptr [rbp-0x38] - ;; size=8 bbWeight=2 PerfScore 4.00 + mov rdx, bword ptr [rbp-0x18] + ;; size=4 bbWeight=2 PerfScore 2.00 G_M54707_IG05: - cmp r10d, r9d + cmp r9d, eax jae G_M54707_IG13 - mov r11d, r10d - mov bword ptr [rbp-0x38], rdx + mov r11d, r9d + mov bword ptr [rbp-0x18], rdx mov r11, qword ptr [rdx+8*r11] - mov rax, r8 - mul rdx:rax, r11 - mov r11, qword ptr [rbp-0x18] - add r11, rax - cmp r11, rax - setb al - movzx rax, al - add rax, rdx - mov qword ptr [rbp-0x20], rax + mov rdx, r8 + mulx r11, rdx, r11 + add r10, rdx + cmp r10, rdx + setb dl + movzx rdx, dl + add r11, rdx + cmp r9d, esi + jae G_M54707_IG13 + mov edx, r9d + mov qword ptr [rdi+8*rdx], r10 + lea r10d, [r9+0x01] + cmp r10d, eax + jae G_M54707_IG13 + mov ebx, r10d + mov rdx, bword ptr [rbp-0x18] + mov r15, qword ptr [rdx+8*rbx] + mov rdx, r8 + mulx r15, rdx, r15 + add r11, rdx + cmp r11, rdx + setb dl + movzx rdx, dl + add r15, rdx cmp r10d, esi jae G_M54707_IG13 - mov edx, r10d - mov qword ptr [rdi+8*rdx], r11 - lea r11d, [r10+0x01] - cmp r11d, r9d + mov qword ptr [rdi+8*rbx], r11 + lea r10d, [r9+0x02] + cmp r10d, eax jae G_M54707_IG13 - mov ebx, r11d - mov rdx, bword ptr [rbp-0x38] - mov r15, qword ptr [rdx+8*rbx] - mov rax, r8 - mul rdx:rax, r15 - mov r15, qword ptr [rbp-0x20] - add r15, rax - cmp r15, rax - setb al - movzx rax, al - add rax, rdx - mov qword ptr [rbp-0x28], rax - cmp r11d, esi + mov r11d, r10d + mov rdx, bword ptr [rbp-0x18] + mov rbx, qword ptr [rdx+8*r11] + mov rdx, r8 + mulx rbx, rdx, rbx + add r15, rdx + cmp r15, rdx + setb dl + movzx rdx, dl + add rbx, rdx + cmp r10d, esi jae G_M54707_IG13 - mov qword ptr [rdi+8*rbx], r15 - lea r11d, [r10+0x02] - cmp r11d, r9d + mov qword ptr [rdi+8*r11], r15 + lea r10d, [r9+0x03] + cmp r10d, eax jae G_M54707_IG13 - mov ebx, r11d - mov rdx, bword ptr [rbp-0x38] - mov r15, qword ptr [rdx+8*rbx] - mov rax, r8 - mul rdx:rax, r15 - mov r15, qword ptr [rbp-0x28] - add r15, rax - cmp r15, rax - setb al - movzx rax, al - add rax, rdx - mov qword ptr [rbp-0x30], rax - cmp r11d, esi - jae G_M54707_IG13 - mov qword ptr [rdi+8*rbx], r15 - lea r11d, [r10+0x03] - cmp r11d, r9d - jae G_M54707_IG13 - mov ebx, r11d - mov rdx, bword ptr [rbp-0x38] - mov r15, qword ptr [rdx+8*rbx] - mov rax, r8 - ;; size=224 bbWeight=4 PerfScore 188.00 + mov r11d, r10d + mov rdx, bword ptr [rbp-0x18] + mov r15, qword ptr [rdx+8*r11] + mov rdx, r8 + mulx r15, rdx, r15 + add rbx, rdx + cmp rbx, rdx + setb dl + movzx rdx, dl + add rdx, r15 + cmp r10d, esi + ;; size=229 bbWeight=4 PerfScore 183.00 G_M54707_IG06: - mul rdx:rax, r15 - mov r15, qword ptr [rbp-0x30] - add r15, rax - cmp r15, rax - setb al - movzx rax, al - add rax, rdx - cmp r11d, esi jae G_M54707_IG13 - mov qword ptr [rdi+8*rbx], r15 - mov r11, rax - add r10d, 4 - lea eax, [r10+0x03] - cmp eax, ecx + mov qword ptr [rdi+8*r11], rbx + mov r10, rdx + add r9d, 4 + lea edx, [r9+0x03] + cmp edx, ecx jl G_M54707_IG04 - ;; size=54 bbWeight=4 PerfScore 40.00 + ;; size=29 bbWeight=4 PerfScore 17.00 G_M54707_IG07: - cmp r10d, ecx + cmp r9d, ecx jge SHORT G_M54707_IG10 ;; size=5 bbWeight=0.50 PerfScore 0.62 G_M54707_IG08: - test r10d, r10d + test r9d, r9d jl SHORT G_M54707_IG12 cmp ecx, esi jg SHORT G_M54707_IG12 ;; size=9 bbWeight=0.25 PerfScore 0.62 G_M54707_IG09: - mov eax, r10d - mov rdx, bword ptr [rbp-0x38] - mov rsi, qword ptr [rdx+8*rax] - mov rax, r8 - mul rdx:rax, rsi - lea rcx, [rax+r11] - cmp rcx, rax - setb r11b - movzx r11, r11b - add r11, rdx - mov esi, r10d - mov qword ptr [rdi+8*rsi], rcx - inc r10d - cmp r10d, r9d + mov edx, r9d + mov r11, bword ptr [rbp-0x18] + mov rdx, qword ptr [r11+8*rdx] + mulx rcx, rsi, r8 + lea rbx, [rsi+r10] + cmp rbx, rsi + setb r10b + movzx r10, r10b + add r10, rcx + mov edx, r9d + mov qword ptr [rdi+8*rdx], rbx + inc r9d + cmp r9d, eax + mov bword ptr [rbp-0x18], r11 jl SHORT G_M54707_IG09 - ;; size=50 bbWeight=3.96 PerfScore 43.56 + ;; size=53 bbWeight=3.96 PerfScore 46.53 G_M54707_IG10: - mov rax, r11 + mov rax, r10 ;; size=3 bbWeight=1 PerfScore 0.25 G_M54707_IG11: - add rsp, 48 + add rsp, 16 pop rbx pop r15 pop rbp ret ;; size=9 bbWeight=1 PerfScore 2.75 G_M54707_IG12: - cmp r10d, r9d + cmp r9d, eax jae SHORT G_M54707_IG13 - mov eax, r10d - mov rdx, bword ptr [rbp-0x38] - mov rax, qword ptr [rdx+8*rax] - mul rdx:rax, r8 - add r11, rax - cmp r11, rax - setb al - movzx rax, al - add rax, rdx - cmp r10d, esi + mov edx, r9d + mov r11, bword ptr [rbp-0x18] + mov rdx, qword ptr [r11+8*rdx] + mulx rbx, rdx, r8 + add r10, rdx + cmp r10, rdx + setb dl + movzx rdx, dl + add rdx, rbx + cmp r9d, esi jae SHORT G_M54707_IG13 - mov edx, r10d - mov qword ptr [rdi+8*rdx], r11 - mov r11, rax - inc r10d - cmp r10d, ecx + mov ebx, r9d + mov qword ptr [rdi+8*rbx], r10 + mov r10, rdx + inc r9d + cmp r9d, ecx + mov bword ptr [rbp-0x18], r11 jl SHORT G_M54707_IG12 jmp SHORT G_M54707_IG10 - ;; size=59 bbWeight=0.04 PerfScore 0.61 + ;; size=65 bbWeight=0.04 PerfScore 0.65 G_M54707_IG13: call CORINFO_HELP_RNGCHKFAIL int3 ;; size=6 bbWeight=0 PerfScore 0.00 -; Total bytes of code 470, prolog size 13, PerfScore 289.17, instruction count 142, allocated bytes for code 470 (MethodHash=4ae62a4c) for method System.Numerics.BigIntegerCalculator:Mul1(System.Span`1[nuint],System.ReadOnlySpan`1[nuint],nuint):nuint (FullOpts) +; Total bytes of code 447, prolog size 13, PerfScore 260.68, instruction count 133, allocated bytes for code 447 (MethodHash=4ae62a4c) for method System.Numerics.BigIntegerCalculator:Mul1(System.Span`1[nuint],System.ReadOnlySpan`1[nuint],nuint):nuint (FullOpts) ; ============================================================ ```
-23 (-4.89 % of base) - System.Numerics.BigIntegerCalculator:Mul1(System.Span`1[nuint],System.ReadOnlySpan`1[nuint],nuint):nuint ```diff ; Assembly listing for method System.Numerics.BigIntegerCalculator:Mul1(System.Span`1[nuint],System.ReadOnlySpan`1[nuint],nuint):nuint (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rbp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 76 single block inlinees; 10 inlinees without PGO data ; Final local variable assignments ; ;* V00 arg0 [V00 ] ( 0, 0 ) struct (16) zero-ref multireg-arg ld-addr-op single-def ;* V01 arg1 [V01 ] ( 0, 0 ) struct (16) zero-ref multireg-arg ld-addr-op single-def ; V02 arg2 [V02,T01] ( 8, 22 ) long -> r8 single-def -; V03 loc0 [V03,T04] ( 7, 21 ) int -> r9 -; V04 loc1 [V04,T00] ( 25, 61.83) int -> r10 -; V05 loc2 [V05,T06] ( 8, 18 ) long -> [rbp-0x18] +; V03 loc0 [V03,T04] ( 7, 21 ) int -> rax +; V04 loc1 [V04,T00] ( 25, 61.83) int -> r9 +; V05 loc2 [V05,T06] ( 8, 18 ) long -> r10 ;* V06 loc3 [V06 ] ( 0, 0 ) struct (16) zero-ref ;* V07 loc4 [V07 ] ( 0, 0 ) struct (16) zero-ref ;* V08 loc5 [V08 ] ( 0, 0 ) struct (16) zero-ref ;* V09 loc6 [V09 ] ( 0, 0 ) struct (16) zero-ref ;* V10 loc7 [V10 ] ( 0, 0 ) struct (16) zero-ref ;* V11 loc8 [V11 ] ( 0, 0 ) long -> zero-ref ;# V12 OutArgs [V12 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ;* V13 tmp1 [V13 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V14 tmp2 [V14 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V15 tmp3 [V15 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V16 tmp4 [V16 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V17 tmp5 [V17 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V18 tmp6 [V18 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V19 tmp7 [V19 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V20 tmp8 [V20 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V21 tmp9 [V21 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V22 tmp10 [V22 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V23 tmp11 [V23 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V24 tmp12 [V24 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V25 tmp13 [V25 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V26 tmp14 [V26 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V27 tmp15 [V27 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V28 tmp16 [V28 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V29 tmp17 [V29 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V30 tmp18 [V30 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V31 tmp19 [V31 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V32 tmp20 [V32 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V33 tmp21 [V33 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V34 tmp22 [V34 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V35 tmp23 [V35 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V36 tmp24 [V36 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V37 tmp25 [V37 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V38 tmp26 [V38 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V39 tmp27 [V39 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V40 tmp28 [V40 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V41 tmp29 [V41 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V42 tmp30 [V42 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V43 tmp31 [V43 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V44 tmp32 [V44 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V45 tmp33 [V45 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V46 tmp34 [V46 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V47 tmp35 [V47 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V48 tmp36 [V48 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V49 tmp37 [V49 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V50 tmp38 [V50 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V51 tmp39 [V51 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V52 tmp40 [V52 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V53 tmp41 [V53 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V54 tmp42 [V54 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V55 tmp43 [V55 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" -; V56 tmp44 [V56,T12] ( 3, 12 ) long -> r11 "Inline stloc first use temp" -; V57 tmp45 [V57,T28] ( 2, 8 ) long -> rax "Inline stloc first use temp" +; V56 tmp44 [V56,T12] ( 3, 12 ) long -> r10 "Inline stloc first use temp" +; V57 tmp45 [V57,T28] ( 2, 8 ) long -> rdx "Inline stloc first use temp" ;* V58 tmp46 [V58 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V59 tmp47 [V59 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V60 tmp48 [V60 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V61 tmp49 [V61 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V62 tmp50 [V62 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V63 tmp51 [V63 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V64 tmp52 [V64 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V65 tmp53 [V65 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V66 tmp54 [V66 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V67 tmp55 [V67 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V68 tmp56 [V68 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V69 tmp57 [V69 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V70 tmp58 [V70 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V71 tmp59 [V71 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V72 tmp60 [V72 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V73 tmp61 [V73 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V74 tmp62 [V74 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V75 tmp63 [V75 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V76 tmp64 [V76 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V77 tmp65 [V77 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V78 tmp66 [V78 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V79 tmp67 [V79 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V80 tmp68 [V80 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V81 tmp69 [V81 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" -; V82 tmp70 [V82,T13] ( 3, 12 ) long -> r15 "Inline stloc first use temp" -; V83 tmp71 [V83,T29] ( 2, 8 ) long -> rax "Inline stloc first use temp" +; V82 tmp70 [V82,T13] ( 3, 12 ) long -> r11 "Inline stloc first use temp" +; V83 tmp71 [V83,T29] ( 2, 8 ) long -> rdx "Inline stloc first use temp" ;* V84 tmp72 [V84 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V85 tmp73 [V85 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V86 tmp74 [V86 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V87 tmp75 [V87 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V88 tmp76 [V88 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V89 tmp77 [V89 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V90 tmp78 [V90 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V91 tmp79 [V91 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V92 tmp80 [V92 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V93 tmp81 [V93 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V94 tmp82 [V94 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V95 tmp83 [V95 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V96 tmp84 [V96 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V97 tmp85 [V97 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V98 tmp86 [V98 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V99 tmp87 [V99 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V100 tmp88 [V100 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V101 tmp89 [V101 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V102 tmp90 [V102 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V103 tmp91 [V103 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V104 tmp92 [V104 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V105 tmp93 [V105 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V106 tmp94 [V106 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V107 tmp95 [V107 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V108 tmp96 [V108,T14] ( 3, 12 ) long -> r15 "Inline stloc first use temp" -; V109 tmp97 [V109,T30] ( 2, 8 ) long -> rax "Inline stloc first use temp" +; V109 tmp97 [V109,T30] ( 2, 8 ) long -> rdx "Inline stloc first use temp" ;* V110 tmp98 [V110 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V111 tmp99 [V111 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V112 tmp100 [V112 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V113 tmp101 [V113 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V114 tmp102 [V114 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V115 tmp103 [V115 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V116 tmp104 [V116 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V117 tmp105 [V117 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V118 tmp106 [V118 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V119 tmp107 [V119 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V120 tmp108 [V120 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V121 tmp109 [V121 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V122 tmp110 [V122 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V123 tmp111 [V123 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V124 tmp112 [V124 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V125 tmp113 [V125 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V126 tmp114 [V126 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V127 tmp115 [V127 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V128 tmp116 [V128 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V129 tmp117 [V129 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V130 tmp118 [V130 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V131 tmp119 [V131 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V132 tmp120 [V132 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V133 tmp121 [V133 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" -; V134 tmp122 [V134,T15] ( 3, 12 ) long -> r15 "Inline stloc first use temp" -; V135 tmp123 [V135,T31] ( 2, 8 ) long -> rax "Inline stloc first use temp" +; V134 tmp122 [V134,T15] ( 3, 12 ) long -> rbx "Inline stloc first use temp" +; V135 tmp123 [V135,T31] ( 2, 8 ) long -> rdx "Inline stloc first use temp" ;* V136 tmp124 [V136 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V137 tmp125 [V137 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V138 tmp126 [V138 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V139 tmp127 [V139 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V140 tmp128 [V140 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V141 tmp129 [V141 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V142 tmp130 [V142 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V143 tmp131 [V143 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V144 tmp132 [V144 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V145 tmp133 [V145 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V146 tmp134 [V146 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V147 tmp135 [V147 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V148 tmp136 [V148 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V149 tmp137 [V149 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V150 tmp138 [V150 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V151 tmp139 [V151 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V152 tmp140 [V152 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V153 tmp141 [V153 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V154 tmp142 [V154 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V155 tmp143 [V155 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V156 tmp144 [V156 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V157 tmp145 [V157 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ; V158 tmp146 [V158,T10] ( 6, 12 ) long -> registers "Inline stloc first use temp" ; V159 tmp147 [V159,T24] ( 4, 8 ) long -> registers "Inline stloc first use temp" ;* V160 tmp148 [V160 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V161 tmp149 [V161 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V162 tmp150 [V162 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V163 tmp151 [V163 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V164 tmp152 [V164 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V165 tmp153 [V165 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V166 tmp154 [V166 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V167 tmp155 [V167 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V168 tmp156 [V168 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V169 tmp157 [V169,T02] ( 7, 21 ) byref -> rdi single-def "field V00._reference (fldOffset=0x0)" P-INDEP ; V170 tmp158 [V170,T05] ( 7, 17.29) int -> rsi single-def "field V00._length (fldOffset=0x8)" P-INDEP -; V171 tmp159 [V171,T03] ( 7, 21 ) byref -> [rbp-0x38] single-def "field V01._reference (fldOffset=0x0)" P-INDEP +; V171 tmp159 [V171,T03] ( 7, 21 ) byref -> [rbp-0x18] single-def "field V01._reference (fldOffset=0x0)" P-INDEP ; V172 tmp160 [V172,T23] ( 7, 7.79) int -> rcx single-def "field V01._length (fldOffset=0x8)" P-INDEP ;* V173 tmp161 [V173 ] ( 0, 0 ) long -> zero-ref "field V06._lower (fldOffset=0x0)" P-INDEP ;* V174 tmp162 [V174 ] ( 0, 0 ) long -> zero-ref "field V06._upper (fldOffset=0x8)" P-INDEP ;* V175 tmp163 [V175 ] ( 0, 0 ) long -> zero-ref "field V07._lower (fldOffset=0x0)" P-INDEP ;* V176 tmp164 [V176 ] ( 0, 0 ) long -> zero-ref "field V07._upper (fldOffset=0x8)" P-INDEP ;* V177 tmp165 [V177 ] ( 0, 0 ) long -> zero-ref "field V08._lower (fldOffset=0x0)" P-INDEP ;* V178 tmp166 [V178 ] ( 0, 0 ) long -> zero-ref "field V08._upper (fldOffset=0x8)" P-INDEP ;* V179 tmp167 [V179 ] ( 0, 0 ) long -> zero-ref "field V09._lower (fldOffset=0x0)" P-INDEP ;* V180 tmp168 [V180 ] ( 0, 0 ) long -> zero-ref "field V09._upper (fldOffset=0x8)" P-INDEP ;* V181 tmp169 [V181 ] ( 0, 0 ) long -> zero-ref "field V10._lower (fldOffset=0x0)" P-INDEP ;* V182 tmp170 [V182 ] ( 0, 0 ) long -> zero-ref "field V10._upper (fldOffset=0x8)" P-INDEP ;* V183 tmp171 [V183 ] ( 0, 0 ) long -> zero-ref "field V13._lower (fldOffset=0x0)" P-INDEP ;* V184 tmp172 [V184 ] ( 0, 0 ) long -> zero-ref "field V13._upper (fldOffset=0x8)" P-INDEP ;* V185 tmp173 [V185 ] ( 0, 0 ) long -> zero-ref "field V14._lower (fldOffset=0x0)" P-INDEP ;* V186 tmp174 [V186 ] ( 0, 0 ) long -> zero-ref "field V14._upper (fldOffset=0x8)" P-INDEP ;* V187 tmp175 [V187 ] ( 0, 0 ) long -> zero-ref "field V15._lower (fldOffset=0x0)" P-INDEP ;* V188 tmp176 [V188 ] ( 0, 0 ) long -> zero-ref "field V15._upper (fldOffset=0x8)" P-INDEP ;* V189 tmp177 [V189 ] ( 0, 0 ) long -> zero-ref "field V16._lower (fldOffset=0x0)" P-INDEP ;* V190 tmp178 [V190 ] ( 0, 0 ) long -> zero-ref "field V16._upper (fldOffset=0x8)" P-INDEP ;* V191 tmp179 [V191 ] ( 0, 0 ) long -> zero-ref "field V18._lower (fldOffset=0x0)" P-INDEP ;* V192 tmp180 [V192 ] ( 0, 0 ) long -> zero-ref "field V18._upper (fldOffset=0x8)" P-INDEP ;* V193 tmp181 [V193 ] ( 0, 0 ) long -> zero-ref "field V19._lower (fldOffset=0x0)" P-INDEP ;* V194 tmp182 [V194 ] ( 0, 0 ) long -> zero-ref "field V19._upper (fldOffset=0x8)" P-INDEP ;* V195 tmp183 [V195 ] ( 0, 0 ) long -> zero-ref "field V20._lower (fldOffset=0x0)" P-INDEP ;* V196 tmp184 [V196 ] ( 0, 0 ) long -> zero-ref "field V20._upper (fldOffset=0x8)" P-INDEP ;* V197 tmp185 [V197 ] ( 0, 0 ) long -> zero-ref "field V21._lower (fldOffset=0x0)" P-INDEP ;* V198 tmp186 [V198 ] ( 0, 0 ) long -> zero-ref "field V21._upper (fldOffset=0x8)" P-INDEP ;* V199 tmp187 [V199 ] ( 0, 0 ) long -> zero-ref "field V22._lower (fldOffset=0x0)" P-INDEP ;* V200 tmp188 [V200 ] ( 0, 0 ) long -> zero-ref "field V22._upper (fldOffset=0x8)" P-INDEP ;* V201 tmp189 [V201 ] ( 0, 0 ) long -> zero-ref "field V24._lower (fldOffset=0x0)" P-INDEP ;* V202 tmp190 [V202 ] ( 0, 0 ) long -> zero-ref "field V24._upper (fldOffset=0x8)" P-INDEP ;* V203 tmp191 [V203 ] ( 0, 0 ) long -> zero-ref "field V25._lower (fldOffset=0x0)" P-INDEP ;* V204 tmp192 [V204 ] ( 0, 0 ) long -> zero-ref "field V25._upper (fldOffset=0x8)" P-INDEP ;* V205 tmp193 [V205 ] ( 0, 0 ) long -> zero-ref "field V26._lower (fldOffset=0x0)" P-INDEP ;* V206 tmp194 [V206 ] ( 0, 0 ) long -> zero-ref "field V26._upper (fldOffset=0x8)" P-INDEP ;* V207 tmp195 [V207 ] ( 0, 0 ) long -> zero-ref "field V27._lower (fldOffset=0x0)" P-INDEP ;* V208 tmp196 [V208 ] ( 0, 0 ) long -> zero-ref "field V27._upper (fldOffset=0x8)" P-INDEP ;* V209 tmp197 [V209 ] ( 0, 0 ) long -> zero-ref "field V28._lower (fldOffset=0x0)" P-INDEP ;* V210 tmp198 [V210 ] ( 0, 0 ) long -> zero-ref "field V28._upper (fldOffset=0x8)" P-INDEP ;* V211 tmp199 [V211 ] ( 0, 0 ) long -> zero-ref "field V30._lower (fldOffset=0x0)" P-INDEP ;* V212 tmp200 [V212 ] ( 0, 0 ) long -> zero-ref "field V30._upper (fldOffset=0x8)" P-INDEP ;* V213 tmp201 [V213 ] ( 0, 0 ) long -> zero-ref "field V31._lower (fldOffset=0x0)" P-INDEP ;* V214 tmp202 [V214 ] ( 0, 0 ) long -> zero-ref "field V31._upper (fldOffset=0x8)" P-INDEP ;* V215 tmp203 [V215 ] ( 0, 0 ) long -> zero-ref "field V32._lower (fldOffset=0x0)" P-INDEP ;* V216 tmp204 [V216 ] ( 0, 0 ) long -> zero-ref "field V32._upper (fldOffset=0x8)" P-INDEP ;* V217 tmp205 [V217 ] ( 0, 0 ) long -> zero-ref "field V33._lower (fldOffset=0x0)" P-INDEP ;* V218 tmp206 [V218 ] ( 0, 0 ) long -> zero-ref "field V33._upper (fldOffset=0x8)" P-INDEP ;* V219 tmp207 [V219 ] ( 0, 0 ) long -> zero-ref "field V34._lower (fldOffset=0x0)" P-INDEP ;* V220 tmp208 [V220 ] ( 0, 0 ) long -> zero-ref "field V34._upper (fldOffset=0x8)" P-INDEP ;* V221 tmp209 [V221 ] ( 0, 0 ) long -> zero-ref "field V36._lower (fldOffset=0x0)" P-INDEP ;* V222 tmp210 [V222 ] ( 0, 0 ) long -> zero-ref "field V36._upper (fldOffset=0x8)" P-INDEP ;* V223 tmp211 [V223 ] ( 0, 0 ) long -> zero-ref "field V37._lower (fldOffset=0x0)" P-INDEP ;* V224 tmp212 [V224 ] ( 0, 0 ) long -> zero-ref "field V37._upper (fldOffset=0x8)" P-INDEP ;* V225 tmp213 [V225 ] ( 0, 0 ) long -> zero-ref "field V38._lower (fldOffset=0x0)" P-INDEP ;* V226 tmp214 [V226 ] ( 0, 0 ) long -> zero-ref "field V38._upper (fldOffset=0x8)" P-INDEP ;* V227 tmp215 [V227 ] ( 0, 0 ) long -> zero-ref "field V39._lower (fldOffset=0x0)" P-INDEP ;* V228 tmp216 [V228 ] ( 0, 0 ) long -> zero-ref "field V39._upper (fldOffset=0x8)" P-INDEP ;* V229 tmp217 [V229 ] ( 0, 0 ) long -> zero-ref "field V40._lower (fldOffset=0x0)" P-INDEP ;* V230 tmp218 [V230 ] ( 0, 0 ) long -> zero-ref "field V40._upper (fldOffset=0x8)" P-INDEP ;* V231 tmp219 [V231 ] ( 0, 0 ) long -> zero-ref "field V42._lower (fldOffset=0x0)" P-INDEP ;* V232 tmp220 [V232 ] ( 0, 0 ) long -> zero-ref "field V42._upper (fldOffset=0x8)" P-INDEP ; V233 tmp221 [V233,T32] ( 2, 8 ) long -> r11 "field V44._lower (fldOffset=0x0)" P-INDEP ;* V234 tmp222 [V234 ] ( 0, 0 ) long -> zero-ref "field V44._upper (fldOffset=0x8)" P-INDEP ;* V235 tmp223 [V235 ] ( 0, 0 ) long -> zero-ref "field V45._lower (fldOffset=0x0)" P-INDEP ;* V236 tmp224 [V236 ] ( 0, 0 ) long -> zero-ref "field V45._upper (fldOffset=0x8)" P-INDEP ;* V237 tmp225 [V237 ] ( 0, 0 ) long -> zero-ref "field V47._lower (fldOffset=0x0)" P-INDEP ;* V238 tmp226 [V238 ] ( 0, 0 ) long -> zero-ref "field V47._upper (fldOffset=0x8)" P-INDEP ;* V239 tmp227 [V239 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V51.Item1 (fldOffset=0x0)" P-DEP ;* V240 tmp228 [V240 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V51.Item2 (fldOffset=0x8)" P-DEP -; V241 tmp229 [V241,T16] ( 3, 12 ) long -> rax "field V52.Item1 (fldOffset=0x0)" P-INDEP -; V242 tmp230 [V242,T33] ( 2, 8 ) long -> rdx "field V52.Item2 (fldOffset=0x8)" P-INDEP +; V241 tmp229 [V241,T16] ( 3, 12 ) long -> rdx "field V52.Item1 (fldOffset=0x0)" P-INDEP +; V242 tmp230 [V242,T33] ( 2, 8 ) long -> r11 "field V52.Item2 (fldOffset=0x8)" P-INDEP ;* V243 tmp231 [V243 ] ( 0, 0 ) long -> zero-ref "field V55._lower (fldOffset=0x0)" P-INDEP ;* V244 tmp232 [V244 ] ( 0, 0 ) long -> zero-ref "field V55._upper (fldOffset=0x8)" P-INDEP ;* V245 tmp233 [V245 ] ( 0, 0 ) long -> zero-ref "field V58._lower (fldOffset=0x0)" P-INDEP -; V246 tmp234 [V246,T34] ( 2, 8 ) long -> [rbp-0x20] spill-single-def "field V58._upper (fldOffset=0x8)" P-INDEP +; V246 tmp234 [V246,T34] ( 2, 8 ) long -> r11 "field V58._upper (fldOffset=0x8)" P-INDEP ; V247 tmp235 [V247,T35] ( 2, 8 ) long -> r15 "field V61._lower (fldOffset=0x0)" P-INDEP ;* V248 tmp236 [V248 ] ( 0, 0 ) long -> zero-ref "field V61._upper (fldOffset=0x8)" P-INDEP ;* V249 tmp237 [V249 ] ( 0, 0 ) long -> zero-ref "field V62._lower (fldOffset=0x0)" P-INDEP ;* V250 tmp238 [V250 ] ( 0, 0 ) long -> zero-ref "field V62._upper (fldOffset=0x8)" P-INDEP ;* V251 tmp239 [V251 ] ( 0, 0 ) long -> zero-ref "field V64._lower (fldOffset=0x0)" P-INDEP ;* V252 tmp240 [V252 ] ( 0, 0 ) long -> zero-ref "field V64._upper (fldOffset=0x8)" P-INDEP ;* V253 tmp241 [V253 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V68.Item1 (fldOffset=0x0)" P-DEP ;* V254 tmp242 [V254 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V68.Item2 (fldOffset=0x8)" P-DEP -; V255 tmp243 [V255,T17] ( 3, 12 ) long -> rax "field V69.Item1 (fldOffset=0x0)" P-INDEP -; V256 tmp244 [V256,T36] ( 2, 8 ) long -> rdx "field V69.Item2 (fldOffset=0x8)" P-INDEP +; V255 tmp243 [V255,T17] ( 3, 12 ) long -> rdx "field V69.Item1 (fldOffset=0x0)" P-INDEP +; V256 tmp244 [V256,T36] ( 2, 8 ) long -> r15 "field V69.Item2 (fldOffset=0x8)" P-INDEP ;* V257 tmp245 [V257 ] ( 0, 0 ) long -> zero-ref "field V72._lower (fldOffset=0x0)" P-INDEP ;* V258 tmp246 [V258 ] ( 0, 0 ) long -> zero-ref "field V72._upper (fldOffset=0x8)" P-INDEP ;* V259 tmp247 [V259 ] ( 0, 0 ) long -> zero-ref "field V75._lower (fldOffset=0x0)" P-INDEP ;* V260 tmp248 [V260 ] ( 0, 0 ) long -> zero-ref "field V75._upper (fldOffset=0x8)" P-INDEP ;* V261 tmp249 [V261 ] ( 0, 0 ) long -> zero-ref "field V77._lower (fldOffset=0x0)" P-INDEP ;* V262 tmp250 [V262 ] ( 0, 0 ) long -> zero-ref "field V77._upper (fldOffset=0x8)" P-INDEP ;* V263 tmp251 [V263 ] ( 0, 0 ) long -> zero-ref "field V80._lower (fldOffset=0x0)" P-INDEP ;* V264 tmp252 [V264 ] ( 0, 0 ) long -> zero-ref "field V80._upper (fldOffset=0x8)" P-INDEP ;* V265 tmp253 [V265 ] ( 0, 0 ) long -> zero-ref "field V84._lower (fldOffset=0x0)" P-INDEP -; V266 tmp254 [V266,T37] ( 2, 8 ) long -> [rbp-0x28] spill-single-def "field V84._upper (fldOffset=0x8)" P-INDEP -; V267 tmp255 [V267,T38] ( 2, 8 ) long -> r15 "field V87._lower (fldOffset=0x0)" P-INDEP +; V266 tmp254 [V266,T37] ( 2, 8 ) long -> r15 "field V84._upper (fldOffset=0x8)" P-INDEP +; V267 tmp255 [V267,T38] ( 2, 8 ) long -> rbx "field V87._lower (fldOffset=0x0)" P-INDEP ;* V268 tmp256 [V268 ] ( 0, 0 ) long -> zero-ref "field V87._upper (fldOffset=0x8)" P-INDEP ;* V269 tmp257 [V269 ] ( 0, 0 ) long -> zero-ref "field V88._lower (fldOffset=0x0)" P-INDEP ;* V270 tmp258 [V270 ] ( 0, 0 ) long -> zero-ref "field V88._upper (fldOffset=0x8)" P-INDEP ;* V271 tmp259 [V271 ] ( 0, 0 ) long -> zero-ref "field V90._lower (fldOffset=0x0)" P-INDEP ;* V272 tmp260 [V272 ] ( 0, 0 ) long -> zero-ref "field V90._upper (fldOffset=0x8)" P-INDEP ;* V273 tmp261 [V273 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V94.Item1 (fldOffset=0x0)" P-DEP ;* V274 tmp262 [V274 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V94.Item2 (fldOffset=0x8)" P-DEP -; V275 tmp263 [V275,T18] ( 3, 12 ) long -> rax "field V95.Item1 (fldOffset=0x0)" P-INDEP -; V276 tmp264 [V276,T39] ( 2, 8 ) long -> rdx "field V95.Item2 (fldOffset=0x8)" P-INDEP +; V275 tmp263 [V275,T18] ( 3, 12 ) long -> rdx "field V95.Item1 (fldOffset=0x0)" P-INDEP +; V276 tmp264 [V276,T39] ( 2, 8 ) long -> rbx "field V95.Item2 (fldOffset=0x8)" P-INDEP ;* V277 tmp265 [V277 ] ( 0, 0 ) long -> zero-ref "field V98._lower (fldOffset=0x0)" P-INDEP ;* V278 tmp266 [V278 ] ( 0, 0 ) long -> zero-ref "field V98._upper (fldOffset=0x8)" P-INDEP ;* V279 tmp267 [V279 ] ( 0, 0 ) long -> zero-ref "field V101._lower (fldOffset=0x0)" P-INDEP ;* V280 tmp268 [V280 ] ( 0, 0 ) long -> zero-ref "field V101._upper (fldOffset=0x8)" P-INDEP ;* V281 tmp269 [V281 ] ( 0, 0 ) long -> zero-ref "field V103._lower (fldOffset=0x0)" P-INDEP ;* V282 tmp270 [V282 ] ( 0, 0 ) long -> zero-ref "field V103._upper (fldOffset=0x8)" P-INDEP ;* V283 tmp271 [V283 ] ( 0, 0 ) long -> zero-ref "field V106._lower (fldOffset=0x0)" P-INDEP ;* V284 tmp272 [V284 ] ( 0, 0 ) long -> zero-ref "field V106._upper (fldOffset=0x8)" P-INDEP ;* V285 tmp273 [V285 ] ( 0, 0 ) long -> zero-ref "field V110._lower (fldOffset=0x0)" P-INDEP -; V286 tmp274 [V286,T40] ( 2, 8 ) long -> [rbp-0x30] spill-single-def "field V110._upper (fldOffset=0x8)" P-INDEP +; V286 tmp274 [V286,T40] ( 2, 8 ) long -> rbx "field V110._upper (fldOffset=0x8)" P-INDEP ; V287 tmp275 [V287,T41] ( 2, 8 ) long -> r15 "field V113._lower (fldOffset=0x0)" P-INDEP ;* V288 tmp276 [V288 ] ( 0, 0 ) long -> zero-ref "field V113._upper (fldOffset=0x8)" P-INDEP ;* V289 tmp277 [V289 ] ( 0, 0 ) long -> zero-ref "field V114._lower (fldOffset=0x0)" P-INDEP ;* V290 tmp278 [V290 ] ( 0, 0 ) long -> zero-ref "field V114._upper (fldOffset=0x8)" P-INDEP ;* V291 tmp279 [V291 ] ( 0, 0 ) long -> zero-ref "field V116._lower (fldOffset=0x0)" P-INDEP ;* V292 tmp280 [V292 ] ( 0, 0 ) long -> zero-ref "field V116._upper (fldOffset=0x8)" P-INDEP ;* V293 tmp281 [V293 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V120.Item1 (fldOffset=0x0)" P-DEP ;* V294 tmp282 [V294 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V120.Item2 (fldOffset=0x8)" P-DEP -; V295 tmp283 [V295,T19] ( 3, 12 ) long -> rax "field V121.Item1 (fldOffset=0x0)" P-INDEP -; V296 tmp284 [V296,T42] ( 2, 8 ) long -> rdx "field V121.Item2 (fldOffset=0x8)" P-INDEP +; V295 tmp283 [V295,T19] ( 3, 12 ) long -> rdx "field V121.Item1 (fldOffset=0x0)" P-INDEP +; V296 tmp284 [V296,T42] ( 2, 8 ) long -> r15 "field V121.Item2 (fldOffset=0x8)" P-INDEP ;* V297 tmp285 [V297 ] ( 0, 0 ) long -> zero-ref "field V124._lower (fldOffset=0x0)" P-INDEP ;* V298 tmp286 [V298 ] ( 0, 0 ) long -> zero-ref "field V124._upper (fldOffset=0x8)" P-INDEP ;* V299 tmp287 [V299 ] ( 0, 0 ) long -> zero-ref "field V127._lower (fldOffset=0x0)" P-INDEP ;* V300 tmp288 [V300 ] ( 0, 0 ) long -> zero-ref "field V127._upper (fldOffset=0x8)" P-INDEP ;* V301 tmp289 [V301 ] ( 0, 0 ) long -> zero-ref "field V129._lower (fldOffset=0x0)" P-INDEP ;* V302 tmp290 [V302 ] ( 0, 0 ) long -> zero-ref "field V129._upper (fldOffset=0x8)" P-INDEP ;* V303 tmp291 [V303 ] ( 0, 0 ) long -> zero-ref "field V132._lower (fldOffset=0x0)" P-INDEP ;* V304 tmp292 [V304 ] ( 0, 0 ) long -> zero-ref "field V132._upper (fldOffset=0x8)" P-INDEP ;* V305 tmp293 [V305 ] ( 0, 0 ) long -> zero-ref "field V136._lower (fldOffset=0x0)" P-INDEP -; V306 tmp294 [V306,T43] ( 2, 8 ) long -> rax "field V136._upper (fldOffset=0x8)" P-INDEP +; V306 tmp294 [V306,T43] ( 2, 8 ) long -> rdx "field V136._upper (fldOffset=0x8)" P-INDEP ;* V307 tmp295 [V307 ] ( 0, 0 ) long -> zero-ref "field V138._lower (fldOffset=0x0)" P-INDEP ;* V308 tmp296 [V308 ] ( 0, 0 ) long -> zero-ref "field V138._upper (fldOffset=0x8)" P-INDEP ;* V309 tmp297 [V309 ] ( 0, 0 ) long -> zero-ref "field V141._lower (fldOffset=0x0)" P-INDEP ;* V310 tmp298 [V310 ] ( 0, 0 ) long -> zero-ref "field V141._upper (fldOffset=0x8)" P-INDEP ;* V311 tmp299 [V311 ] ( 0, 0 ) long -> zero-ref "field V143._lower (fldOffset=0x0)" P-INDEP ;* V312 tmp300 [V312 ] ( 0, 0 ) long -> zero-ref "field V143._upper (fldOffset=0x8)" P-INDEP -; V313 tmp301 [V313,T25] ( 4, 8 ) long -> registers "field V146._lower (fldOffset=0x0)" P-INDEP +; V313 tmp301 [V313,T25] ( 4, 8 ) long -> rdx "field V146._lower (fldOffset=0x0)" P-INDEP ;* V314 tmp302 [V314 ] ( 0, 0 ) long -> zero-ref "field V146._upper (fldOffset=0x8)" P-INDEP ;* V315 tmp303 [V315 ] ( 0, 0 ) long -> zero-ref "field V147._lower (fldOffset=0x0)" P-INDEP ;* V316 tmp304 [V316 ] ( 0, 0 ) long -> zero-ref "field V147._upper (fldOffset=0x8)" P-INDEP ;* V317 tmp305 [V317 ] ( 0, 0 ) long -> zero-ref "field V149._lower (fldOffset=0x0)" P-INDEP ;* V318 tmp306 [V318 ] ( 0, 0 ) long -> zero-ref "field V149._upper (fldOffset=0x8)" P-INDEP ;* V319 tmp307 [V319 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V153.Item1 (fldOffset=0x0)" P-DEP ;* V320 tmp308 [V320 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V153.Item2 (fldOffset=0x8)" P-DEP -; V321 tmp309 [V321,T11] ( 6, 12 ) long -> rax "field V154.Item1 (fldOffset=0x0)" P-INDEP -; V322 tmp310 [V322,T26] ( 4, 8 ) long -> rdx "field V154.Item2 (fldOffset=0x8)" P-INDEP +; V321 tmp309 [V321,T11] ( 6, 12 ) long -> registers "field V154.Item1 (fldOffset=0x0)" P-INDEP +; V322 tmp310 [V322,T26] ( 4, 8 ) long -> registers "field V154.Item2 (fldOffset=0x8)" P-INDEP ;* V323 tmp311 [V323 ] ( 0, 0 ) long -> zero-ref "field V157._lower (fldOffset=0x0)" P-INDEP ;* V324 tmp312 [V324 ] ( 0, 0 ) long -> zero-ref "field V157._upper (fldOffset=0x8)" P-INDEP ;* V325 tmp313 [V325 ] ( 0, 0 ) long -> zero-ref "field V160._lower (fldOffset=0x0)" P-INDEP ; V326 tmp314 [V326,T27] ( 4, 8 ) long -> registers "field V160._upper (fldOffset=0x8)" P-INDEP ;* V327 tmp315 [V327 ] ( 0, 0 ) long -> zero-ref "field V162._lower (fldOffset=0x0)" P-INDEP ;* V328 tmp316 [V328 ] ( 0, 0 ) long -> zero-ref "field V162._upper (fldOffset=0x8)" P-INDEP ;* V329 tmp317 [V329 ] ( 0, 0 ) long -> zero-ref "field V165._lower (fldOffset=0x0)" P-INDEP ;* V330 tmp318 [V330 ] ( 0, 0 ) long -> zero-ref "field V165._upper (fldOffset=0x8)" P-INDEP ;* V331 tmp319 [V331 ] ( 0, 0 ) long -> zero-ref "field V167._lower (fldOffset=0x0)" P-INDEP ;* V332 tmp320 [V332 ] ( 0, 0 ) long -> zero-ref "field V167._upper (fldOffset=0x8)" P-INDEP ; V333 cse0 [V333,T20] ( 3, 12 ) long -> rbx "CSE #03: moderate" -; V334 cse1 [V334,T21] ( 3, 12 ) long -> rbx "CSE #05: moderate" -; V335 cse2 [V335,T22] ( 3, 12 ) long -> rbx "CSE #07: moderate" -; V336 cse3 [V336,T07] ( 4, 16 ) int -> r11 "CSE #02: moderate" -; V337 cse4 [V337,T08] ( 4, 16 ) int -> r11 "CSE #04: moderate" -; V338 cse5 [V338,T09] ( 4, 16 ) int -> r11 "CSE #06: moderate" +; V334 cse1 [V334,T21] ( 3, 12 ) long -> r11 "CSE #05: moderate" +; V335 cse2 [V335,T22] ( 3, 12 ) long -> r11 "CSE #07: moderate" +; V336 cse3 [V336,T07] ( 4, 16 ) int -> r10 "CSE #02: moderate" +; V337 cse4 [V337,T08] ( 4, 16 ) int -> r10 "CSE #04: moderate" +; V338 cse5 [V338,T09] ( 4, 16 ) int -> r10 "CSE #06: moderate" ; -; Lcl frame size = 48 +; Lcl frame size = 16 G_M54707_IG01: push rbp push r15 push rbx - sub rsp, 48 - lea rbp, [rsp+0x40] + sub rsp, 16 + lea rbp, [rsp+0x20] ;; size=13 bbWeight=1 PerfScore 3.75 G_M54707_IG02: - mov r9d, ecx + mov eax, ecx + xor r9d, r9d xor r10d, r10d - xor eax, eax - mov qword ptr [rbp-0x18], rax cmp ecx, 3 jg SHORT G_M54707_IG05 - ;; size=17 bbWeight=1 PerfScore 3.00 + ;; size=13 bbWeight=1 PerfScore 2.00 G_M54707_IG03: - mov bword ptr [rbp-0x38], rdx - mov r11, qword ptr [rbp-0x18] + mov bword ptr [rbp-0x18], rdx jmp G_M54707_IG07 align [0 bytes for IG09] - ;; size=13 bbWeight=0.50 PerfScore 2.00 + ;; size=9 bbWeight=0.50 PerfScore 1.50 G_M54707_IG04: - mov qword ptr [rbp-0x18], r11 - mov rdx, bword ptr [rbp-0x38] - ;; size=8 bbWeight=2 PerfScore 4.00 + mov rdx, bword ptr [rbp-0x18] + ;; size=4 bbWeight=2 PerfScore 2.00 G_M54707_IG05: - cmp r10d, r9d + cmp r9d, eax jae G_M54707_IG13 - mov r11d, r10d - mov bword ptr [rbp-0x38], rdx + mov r11d, r9d + mov bword ptr [rbp-0x18], rdx mov r11, qword ptr [rdx+8*r11] - mov rax, r8 - mul rdx:rax, r11 - mov r11, qword ptr [rbp-0x18] - add r11, rax - cmp r11, rax - setb al - movzx rax, al - add rax, rdx - mov qword ptr [rbp-0x20], rax + mov rdx, r8 + mulx r11, rdx, r11 + add r10, rdx + cmp r10, rdx + setb dl + movzx rdx, dl + add r11, rdx + cmp r9d, esi + jae G_M54707_IG13 + mov edx, r9d + mov qword ptr [rdi+8*rdx], r10 + lea r10d, [r9+0x01] + cmp r10d, eax + jae G_M54707_IG13 + mov ebx, r10d + mov rdx, bword ptr [rbp-0x18] + mov r15, qword ptr [rdx+8*rbx] + mov rdx, r8 + mulx r15, rdx, r15 + add r11, rdx + cmp r11, rdx + setb dl + movzx rdx, dl + add r15, rdx cmp r10d, esi jae G_M54707_IG13 - mov edx, r10d - mov qword ptr [rdi+8*rdx], r11 - lea r11d, [r10+0x01] - cmp r11d, r9d + mov qword ptr [rdi+8*rbx], r11 + lea r10d, [r9+0x02] + cmp r10d, eax jae G_M54707_IG13 - mov ebx, r11d - mov rdx, bword ptr [rbp-0x38] - mov r15, qword ptr [rdx+8*rbx] - mov rax, r8 - mul rdx:rax, r15 - mov r15, qword ptr [rbp-0x20] - add r15, rax - cmp r15, rax - setb al - movzx rax, al - add rax, rdx - mov qword ptr [rbp-0x28], rax - cmp r11d, esi + mov r11d, r10d + mov rdx, bword ptr [rbp-0x18] + mov rbx, qword ptr [rdx+8*r11] + mov rdx, r8 + mulx rbx, rdx, rbx + add r15, rdx + cmp r15, rdx + setb dl + movzx rdx, dl + add rbx, rdx + cmp r10d, esi jae G_M54707_IG13 - mov qword ptr [rdi+8*rbx], r15 - lea r11d, [r10+0x02] - cmp r11d, r9d + mov qword ptr [rdi+8*r11], r15 + lea r10d, [r9+0x03] + cmp r10d, eax jae G_M54707_IG13 - mov ebx, r11d - mov rdx, bword ptr [rbp-0x38] - mov r15, qword ptr [rdx+8*rbx] - mov rax, r8 - mul rdx:rax, r15 - mov r15, qword ptr [rbp-0x28] - add r15, rax - cmp r15, rax - setb al - movzx rax, al - add rax, rdx - mov qword ptr [rbp-0x30], rax - cmp r11d, esi - jae G_M54707_IG13 - mov qword ptr [rdi+8*rbx], r15 - lea r11d, [r10+0x03] - cmp r11d, r9d - jae G_M54707_IG13 - mov ebx, r11d - mov rdx, bword ptr [rbp-0x38] - mov r15, qword ptr [rdx+8*rbx] - mov rax, r8 - ;; size=224 bbWeight=4 PerfScore 188.00 + mov r11d, r10d + mov rdx, bword ptr [rbp-0x18] + mov r15, qword ptr [rdx+8*r11] + mov rdx, r8 + mulx r15, rdx, r15 + add rbx, rdx + cmp rbx, rdx + setb dl + movzx rdx, dl + add rdx, r15 + cmp r10d, esi + ;; size=229 bbWeight=4 PerfScore 183.00 G_M54707_IG06: - mul rdx:rax, r15 - mov r15, qword ptr [rbp-0x30] - add r15, rax - cmp r15, rax - setb al - movzx rax, al - add rax, rdx - cmp r11d, esi jae G_M54707_IG13 - mov qword ptr [rdi+8*rbx], r15 - mov r11, rax - add r10d, 4 - lea eax, [r10+0x03] - cmp eax, ecx + mov qword ptr [rdi+8*r11], rbx + mov r10, rdx + add r9d, 4 + lea edx, [r9+0x03] + cmp edx, ecx jl G_M54707_IG04 - ;; size=54 bbWeight=4 PerfScore 40.00 + ;; size=29 bbWeight=4 PerfScore 17.00 G_M54707_IG07: - cmp r10d, ecx + cmp r9d, ecx jge SHORT G_M54707_IG10 ;; size=5 bbWeight=0.50 PerfScore 0.62 G_M54707_IG08: - test r10d, r10d + test r9d, r9d jl SHORT G_M54707_IG12 cmp ecx, esi jg SHORT G_M54707_IG12 ;; size=9 bbWeight=0.25 PerfScore 0.62 G_M54707_IG09: - mov eax, r10d - mov rdx, bword ptr [rbp-0x38] - mov rsi, qword ptr [rdx+8*rax] - mov rax, r8 - mul rdx:rax, rsi - lea rcx, [rax+r11] - cmp rcx, rax - setb r11b - movzx r11, r11b - add r11, rdx - mov esi, r10d - mov qword ptr [rdi+8*rsi], rcx - inc r10d - cmp r10d, r9d + mov edx, r9d + mov r11, bword ptr [rbp-0x18] + mov rdx, qword ptr [r11+8*rdx] + mulx rcx, rsi, r8 + lea rbx, [rsi+r10] + cmp rbx, rsi + setb r10b + movzx r10, r10b + add r10, rcx + mov edx, r9d + mov qword ptr [rdi+8*rdx], rbx + inc r9d + cmp r9d, eax + mov bword ptr [rbp-0x18], r11 jl SHORT G_M54707_IG09 - ;; size=50 bbWeight=3.96 PerfScore 43.56 + ;; size=53 bbWeight=3.96 PerfScore 46.53 G_M54707_IG10: - mov rax, r11 + mov rax, r10 ;; size=3 bbWeight=1 PerfScore 0.25 G_M54707_IG11: - add rsp, 48 + add rsp, 16 pop rbx pop r15 pop rbp ret ;; size=9 bbWeight=1 PerfScore 2.75 G_M54707_IG12: - cmp r10d, r9d + cmp r9d, eax jae SHORT G_M54707_IG13 - mov eax, r10d - mov rdx, bword ptr [rbp-0x38] - mov rax, qword ptr [rdx+8*rax] - mul rdx:rax, r8 - add r11, rax - cmp r11, rax - setb al - movzx rax, al - add rax, rdx - cmp r10d, esi + mov edx, r9d + mov r11, bword ptr [rbp-0x18] + mov rdx, qword ptr [r11+8*rdx] + mulx rbx, rdx, r8 + add r10, rdx + cmp r10, rdx + setb dl + movzx rdx, dl + add rdx, rbx + cmp r9d, esi jae SHORT G_M54707_IG13 - mov edx, r10d - mov qword ptr [rdi+8*rdx], r11 - mov r11, rax - inc r10d - cmp r10d, ecx + mov ebx, r9d + mov qword ptr [rdi+8*rbx], r10 + mov r10, rdx + inc r9d + cmp r9d, ecx + mov bword ptr [rbp-0x18], r11 jl SHORT G_M54707_IG12 jmp SHORT G_M54707_IG10 - ;; size=59 bbWeight=0.04 PerfScore 0.61 + ;; size=65 bbWeight=0.04 PerfScore 0.65 G_M54707_IG13: call CORINFO_HELP_RNGCHKFAIL int3 ;; size=6 bbWeight=0 PerfScore 0.00 -; Total bytes of code 470, prolog size 13, PerfScore 289.17, instruction count 142, allocated bytes for code 470 (MethodHash=4ae62a4c) for method System.Numerics.BigIntegerCalculator:Mul1(System.Span`1[nuint],System.ReadOnlySpan`1[nuint],nuint):nuint (FullOpts) +; Total bytes of code 447, prolog size 13, PerfScore 260.68, instruction count 133, allocated bytes for code 447 (MethodHash=4ae62a4c) for method System.Numerics.BigIntegerCalculator:Mul1(System.Span`1[nuint],System.ReadOnlySpan`1[nuint],nuint):nuint (FullOpts) ; ============================================================ ```
-21 (-2.20 % of base) - System.Number:DiyFp128EvaluatePositivePolynomial(byref,long,System.ReadOnlySpan`1[System.Number+DiyFp128FixedCoefficient],int,long,byref) ```diff ; Assembly listing for method System.Number:DiyFp128EvaluatePositivePolynomial(byref,long,System.ReadOnlySpan`1[System.Number+DiyFp128FixedCoefficient],int,long,byref) (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rbp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 9 single block inlinees; 8 inlinees without PGO data ; Final local variable assignments ; ; V00 arg0 [V00,T22] ( 5, 5 ) byref -> rdi single-def ; V01 arg1 [V01,T01] ( 29, 74.50) long -> rsi ;* V02 arg2 [V02 ] ( 0, 0 ) struct (16) zero-ref multireg-arg ld-addr-op single-def ; V03 arg3 [V03,T00] ( 24, 76 ) int -> r8 ; V04 arg4 [V04,T02] ( 18, 51.50) long -> r9 ; V05 arg5 [V05,T24] ( 4, 4 ) byref -> [rbp+0x10] single-def -; V06 loc0 [V06,T09] ( 9, 22.50) long -> r11 +; V06 loc0 [V06,T09] ( 9, 22.50) long -> r10 ; V07 loc1 [V07,T23] ( 3, 5.50) long -> [rbp-0x30] spill-single-def ; V08 loc2 [V08,T11] ( 6, 17.50) long -> rdi -; V09 loc3 [V09,T05] ( 20, 49 ) long -> r15 -; V10 loc4 [V10,T04] ( 24, 49 ) long -> r14 -; V11 loc5 [V11,T07] ( 16, 36 ) long -> [rbp-0x38] -; V12 loc6 [V12,T03] ( 20, 52 ) long -> [rbp-0x40] -; V13 loc7 [V13,T12] ( 6, 13.50) long -> r10 +; V09 loc3 [V09,T05] ( 20, 49 ) long -> registers +; V10 loc4 [V10,T04] ( 24, 49 ) long -> registers +; V11 loc5 [V11,T07] ( 16, 36 ) long -> registers +; V12 loc6 [V12,T03] ( 20, 52 ) long -> [rbp-0x38] +; V13 loc7 [V13,T12] ( 6, 13.50) long -> rax ;* V14 loc8 [V14 ] ( 0, 0 ) long -> zero-ref -; V15 loc9 [V15,T06] ( 18, 40.50) long -> r10 -; V16 loc10 [V16,T21] ( 6, 7 ) long -> r13 +; V15 loc9 [V15,T06] ( 18, 40.50) long -> rax +; V16 loc10 [V16,T21] ( 6, 7 ) long -> r14 ;# V17 OutArgs [V17 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ;* V18 tmp1 [V18 ] ( 0, 0 ) struct (24) zero-ref ld-addr-op "NewObj constructor temp" ;* V19 tmp2 [V19 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V20 tmp3 [V20 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V21 tmp4 [V21 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V22 tmp5 [V22 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V23 tmp6 [V23 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V24 tmp7 [V24 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V25 tmp8 [V25 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V26 tmp9 [V26 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V27 tmp10 [V27 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V28 tmp11 [V28 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V29 tmp12 [V29 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V30 tmp13 [V30 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V31 tmp14 [V31 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V32 tmp15 [V32 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V33 tmp16 [V33 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V34 tmp17 [V34 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V35 tmp18 [V35 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V36 tmp19 [V36 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V37 tmp20 [V37 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V38 tmp21 [V38 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V39 tmp22 [V39 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V40 tmp23 [V40 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V41 tmp24 [V41 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V42 tmp25 [V42 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V43 tmp26 [V43 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V44 tmp27 [V44 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V45 tmp28 [V45 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V46 tmp29 [V46 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V47 tmp30 [V47 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V48 tmp31 [V48 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V49 tmp32 [V49 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V50 tmp33 [V50 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V51 tmp34 [V51 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" -; V52 tmp35 [V52,T08] ( 9, 26 ) byref -> [rbp-0x78] single-def "field V02._reference (fldOffset=0x0)" P-INDEP +; V52 tmp35 [V52,T08] ( 9, 26 ) byref -> [rbp-0x58] single-def "field V02._reference (fldOffset=0x0)" P-INDEP ; V53 tmp36 [V53,T10] ( 6, 17.50) int -> rcx single-def "field V02._length (fldOffset=0x8)" P-INDEP ;* V54 tmp37 [V54 ] ( 0, 0 ) int -> zero-ref "field V18._sign (fldOffset=0x0)" P-INDEP ; V55 tmp38 [V55,T30] ( 2, 2 ) int -> rax "field V18._exponent (fldOffset=0x4)" P-INDEP ;* V56 tmp39 [V56 ] ( 0, 0 ) long -> zero-ref "field V18._hi (fldOffset=0x8)" P-INDEP ;* V57 tmp40 [V57 ] ( 0, 0 ) long -> zero-ref "field V18._lo (fldOffset=0x10)" P-INDEP ;* V58 tmp41 [V58 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V21.Item1 (fldOffset=0x0)" P-DEP ;* V59 tmp42 [V59 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V21.Item2 (fldOffset=0x8)" P-DEP -; V60 tmp43 [V60,T25] ( 1, 4 ) long -> rax "field V22.Item1 (fldOffset=0x0)" P-INDEP -; V61 tmp44 [V61,T20] ( 3, 8.50) long -> registers "field V22.Item2 (fldOffset=0x8)" P-INDEP +; V60 tmp43 [V60,T25] ( 1, 4 ) long -> rdx "field V22.Item1 (fldOffset=0x0)" P-INDEP +; V61 tmp44 [V61,T20] ( 3, 8.50) long -> r15 "field V22.Item2 (fldOffset=0x8)" P-INDEP ;* V62 tmp45 [V62 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V25.Item1 (fldOffset=0x0)" P-DEP ;* V63 tmp46 [V63 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V25.Item2 (fldOffset=0x8)" P-DEP -; V64 tmp47 [V64,T26] ( 1, 4 ) long -> rax "field V26.Item1 (fldOffset=0x0)" P-INDEP -; V65 tmp48 [V65,T13] ( 3, 12 ) long -> rdx "field V26.Item2 (fldOffset=0x8)" P-INDEP +; V64 tmp47 [V64,T26] ( 1, 4 ) long -> rdx "field V26.Item1 (fldOffset=0x0)" P-INDEP +; V65 tmp48 [V65,T13] ( 3, 12 ) long -> r13 "field V26.Item2 (fldOffset=0x8)" P-INDEP ;* V66 tmp49 [V66 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V29.Item1 (fldOffset=0x0)" P-DEP ;* V67 tmp50 [V67 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V29.Item2 (fldOffset=0x8)" P-DEP -; V68 tmp51 [V68,T36] ( 1, 0.50) long -> rax "field V30.Item1 (fldOffset=0x0)" P-INDEP -; V69 tmp52 [V69,T31] ( 3, 1.50) long -> [rbp-0x48] spill-single-def "field V30.Item2 (fldOffset=0x8)" P-INDEP +; V68 tmp51 [V68,T36] ( 1, 0.50) long -> r11 "field V30.Item1 (fldOffset=0x0)" P-INDEP +; V69 tmp52 [V69,T31] ( 3, 1.50) long -> [rbp-0x40] spill-single-def "field V30.Item2 (fldOffset=0x8)" P-INDEP ;* V70 tmp53 [V70 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V33.Item1 (fldOffset=0x0)" P-DEP ;* V71 tmp54 [V71 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V33.Item2 (fldOffset=0x8)" P-DEP -; V72 tmp55 [V72,T37] ( 1, 0.50) long -> rax "field V34.Item1 (fldOffset=0x0)" P-INDEP -; V73 tmp56 [V73,T32] ( 3, 1.50) long -> [rbp-0x50] spill-single-def "field V34.Item2 (fldOffset=0x8)" P-INDEP +; V72 tmp55 [V72,T37] ( 1, 0.50) long -> rdx "field V34.Item1 (fldOffset=0x0)" P-INDEP +; V73 tmp56 [V73,T32] ( 3, 1.50) long -> rbx "field V34.Item2 (fldOffset=0x8)" P-INDEP ;* V74 tmp57 [V74 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V37.Item1 (fldOffset=0x0)" P-DEP ;* V75 tmp58 [V75 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V37.Item2 (fldOffset=0x8)" P-DEP -; V76 tmp59 [V76,T38] ( 1, 0.50) long -> rax "field V38.Item1 (fldOffset=0x0)" P-INDEP -; V77 tmp60 [V77,T33] ( 3, 1.50) long -> rdx "field V38.Item2 (fldOffset=0x8)" P-INDEP +; V76 tmp59 [V76,T38] ( 1, 0.50) long -> rdx "field V38.Item1 (fldOffset=0x0)" P-INDEP +; V77 tmp60 [V77,T33] ( 3, 1.50) long -> r15 "field V38.Item2 (fldOffset=0x8)" P-INDEP ;* V78 tmp61 [V78 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V41.Item1 (fldOffset=0x0)" P-DEP ;* V79 tmp62 [V79 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V41.Item2 (fldOffset=0x8)" P-DEP -; V80 tmp63 [V80,T27] ( 1, 4 ) long -> rax "field V42.Item1 (fldOffset=0x0)" P-INDEP -; V81 tmp64 [V81,T14] ( 3, 12 ) long -> [rbp-0x58] spill-single-def "field V42.Item2 (fldOffset=0x8)" P-INDEP +; V80 tmp63 [V80,T27] ( 1, 4 ) long -> rdx "field V42.Item1 (fldOffset=0x0)" P-INDEP +; V81 tmp64 [V81,T14] ( 3, 12 ) long -> rsi "field V42.Item2 (fldOffset=0x8)" P-INDEP ;* V82 tmp65 [V82 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V45.Item1 (fldOffset=0x0)" P-DEP ;* V83 tmp66 [V83 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V45.Item2 (fldOffset=0x8)" P-DEP -; V84 tmp67 [V84,T28] ( 1, 4 ) long -> rax "field V46.Item1 (fldOffset=0x0)" P-INDEP -; V85 tmp68 [V85,T15] ( 3, 12 ) long -> [rbp-0x60] spill-single-def "field V46.Item2 (fldOffset=0x8)" P-INDEP +; V84 tmp67 [V84,T28] ( 1, 4 ) long -> rdx "field V46.Item1 (fldOffset=0x0)" P-INDEP +; V85 tmp68 [V85,T15] ( 3, 12 ) long -> rbx "field V46.Item2 (fldOffset=0x8)" P-INDEP ;* V86 tmp69 [V86 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V49.Item1 (fldOffset=0x0)" P-DEP ;* V87 tmp70 [V87 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V49.Item2 (fldOffset=0x8)" P-DEP -; V88 tmp71 [V88,T29] ( 1, 4 ) long -> rax "field V50.Item1 (fldOffset=0x0)" P-INDEP -; V89 tmp72 [V89,T16] ( 3, 12 ) long -> rdx "field V50.Item2 (fldOffset=0x8)" P-INDEP -; V90 cse0 [V90,T17] ( 3, 12 ) long -> rax "CSE #02: moderate" -; V91 cse1 [V91,T18] ( 3, 12 ) long -> rax "CSE #08: moderate" -; V92 cse2 [V92,T34] ( 3, 1.50) long -> [rbp-0x68] spill-single-def "CSE #05: moderate" -; V93 cse3 [V93,T19] ( 3, 12 ) int -> r14 "CSE #03: moderate" -; V94 cse4 [V94,T35] ( 3, 1.50) int -> [rbp-0x6C] spill-single-def "CSE #06: moderate" +; V88 tmp71 [V88,T29] ( 1, 4 ) long -> rdx "field V50.Item1 (fldOffset=0x0)" P-INDEP +; V89 tmp72 [V89,T16] ( 3, 12 ) long -> rsi "field V50.Item2 (fldOffset=0x8)" P-INDEP +; V90 cse0 [V90,T17] ( 3, 12 ) long -> rdx "CSE #02: moderate" +; V91 cse1 [V91,T18] ( 3, 12 ) long -> rdx "CSE #08: moderate" +; V92 cse2 [V92,T34] ( 3, 1.50) long -> [rbp-0x48] spill-single-def "CSE #05: moderate" +; V93 cse3 [V93,T19] ( 3, 12 ) int -> r15 "CSE #03: moderate" +; V94 cse4 [V94,T35] ( 3, 1.50) int -> [rbp-0x4C] spill-single-def "CSE #06: moderate" ; -; Lcl frame size = 88 +; Lcl frame size = 56 G_M4626_IG01: push rbp push r15 push r14 push r13 push r12 push rbx - sub rsp, 88 - lea rbp, [rsp+0x80] - ;; size=22 bbWeight=1 PerfScore 6.75 + sub rsp, 56 + lea rbp, [rsp+0x60] + ;; size=19 bbWeight=1 PerfScore 6.75 G_M4626_IG02: - mov r11, qword ptr [rdi+0x08] - mov rbx, qword ptr [rdi+0x10] - mov qword ptr [rbp-0x30], rbx + mov r10, qword ptr [rdi+0x08] + mov r11, qword ptr [rdi+0x10] + mov qword ptr [rbp-0x30], r11 movsxd rdi, dword ptr [rdi+0x04] + xor ebx, ebx xor r15d, r15d - xor r14d, r14d cmp rsi, 128 jl SHORT G_M4626_IG04 - align [11 bytes for IG03] - ;; size=42 bbWeight=1 PerfScore 9.00 + align [15 bytes for IG03] + ;; size=45 bbWeight=1 PerfScore 9.00 G_M4626_IG03: add rsi, rdi inc r8d dec r9 cmp rsi, 128 jge SHORT G_M4626_IG03 ;; size=18 bbWeight=4 PerfScore 8.00 G_M4626_IG04: cmp rsi, 64 jge SHORT G_M4626_IG07 ;; size=6 bbWeight=1 PerfScore 1.25 G_M4626_IG05: - mov bword ptr [rbp-0x78], rdx - jmp G_M4626_IG10 + mov bword ptr [rbp-0x58], rdx + jmp SHORT G_M4626_IG10 align [0 bytes for IG08] - ;; size=9 bbWeight=0.50 PerfScore 1.50 + ;; size=6 bbWeight=0.50 PerfScore 1.50 G_M4626_IG06: - mov rdx, bword ptr [rbp-0x78] + mov rdx, bword ptr [rbp-0x58] ;; size=4 bbWeight=2 PerfScore 2.00 G_M4626_IG07: cmp r8d, ecx - jae G_M4626_IG26 - mov eax, r8d - shl rax, 4 - lea r15d, [rsi-0x40] - mov bword ptr [rbp-0x78], rdx - shrx r15, qword ptr [rdx+rax+0x08], r15 + jae G_M4626_IG31 + mov ebx, r8d + shl rbx, 4 + lea r14d, [rsi-0x40] + mov bword ptr [rbp-0x58], rdx + shrx rbx, qword ptr [rdx+rbx+0x08], r14 add rsi, rdi inc r8d dec r9 cmp rsi, 64 jl SHORT G_M4626_IG10 - test r15, r15 + test rbx, rbx je SHORT G_M4626_IG06 ;; size=51 bbWeight=4 PerfScore 39.00 G_M4626_IG08: - mov rax, r15 - mul rdx:rax, r11 + mov rdx, rbx + mulx r15, rdx, r10 cmp r8d, ecx - jae G_M4626_IG26 - mov eax, r8d - shl rax, 4 - lea r15d, [rsi-0x40] - mov r13, bword ptr [rbp-0x78] - shrx r15, qword ptr [r13+rax+0x08], r15 + jae G_M4626_IG31 + mov edx, r8d + shl rdx, 4 + lea ebx, [rsi-0x40] + mov r14, bword ptr [rbp-0x58] + shrx rbx, qword ptr [r14+rdx+0x08], rbx add rsi, rdi inc r8d dec r9 - add r15, rdx + add rbx, r15 cmp rsi, 64 jge SHORT G_M4626_IG08 - ;; size=55 bbWeight=4 PerfScore 48.00 + ;; size=56 bbWeight=4 PerfScore 48.00 G_M4626_IG09: - mov rax, rdx - cmp r15, rax - setb al - movzx rax, al - mov r14d, eax - ;; size=15 bbWeight=0.50 PerfScore 0.75 + cmp rbx, r15 + setb r15b + movzx r15, r15b + ;; size=11 bbWeight=0.50 PerfScore 0.50 G_M4626_IG10: - xor r13d, r13d + xor r14d, r14d test rsi, rsi - jne G_M4626_IG18 + jne G_M4626_IG21 ;; size=12 bbWeight=1 PerfScore 1.50 G_M4626_IG11: - mov r12, bword ptr [rbp-0x78] - ;; size=4 bbWeight=0.50 PerfScore 0.50 + mov r11, qword ptr [rbp-0x30] + mov r12, bword ptr [rbp-0x58] + jmp SHORT G_M4626_IG13 + ;; size=10 bbWeight=0.50 PerfScore 2.00 G_M4626_IG12: - test r9, r9 - jl G_M4626_IG16 - align [0 bytes for IG13] - ;; size=9 bbWeight=2 PerfScore 2.50 + mov r11, qword ptr [rbp-0x30] + ;; size=4 bbWeight=2 PerfScore 2.00 G_M4626_IG13: - mov r10, r14 - imul r10, r11 - cmp r8d, ecx - jae G_M4626_IG26 - mov eax, r8d - shl rax, 4 - mov rdx, qword ptr [r12+rax+0x08] - mov qword ptr [rbp-0x38], rdx - mov rax, qword ptr [r12+rax] - mov qword ptr [rbp-0x40], rax - mov rbx, qword ptr [rbp-0x30] - mov rax, r14 - mul rdx:rax, rbx - mov qword ptr [rbp-0x58], rdx - mov rax, qword ptr [rbp-0x40] - add rax, r10 - mov qword ptr [rbp-0x40], rax - cmp rax, r10 - setb sil - movzx rsi, sil - mov r10d, esi - dec r9 - mov rax, r15 - mul rdx:rax, r11 - mov qword ptr [rbp-0x60], rdx - mov rax, qword ptr [rbp-0x40] - mov rsi, qword ptr [rbp-0x58] - add rax, rsi - mov qword ptr [rbp-0x40], rax - cmp rax, rsi - setb sil - movzx rsi, sil - add rsi, r10 - mov r10, rsi - mov rax, r14 - mul rdx:rax, r11 - mov rax, qword ptr [rbp-0x40] - mov rsi, qword ptr [rbp-0x60] - lea r15, [rax+rsi] - cmp r15, rsi - setb al - movzx rax, al - add rax, r10 - mov r10, rax - add rax, qword ptr [rbp-0x38] - cmp rax, r10 - setb r10b - movzx r10, r10b - inc r8d - lea r14, [rax+rdx] - cmp r14, rdx - setb al - movzx rax, al - add rax, r10 - je SHORT G_M4626_IG15 - ;; size=193 bbWeight=4 PerfScore 162.00 + test r9, r9 + jge SHORT G_M4626_IG16 + ;; size=5 bbWeight=2 PerfScore 2.50 G_M4626_IG14: - shr r15, 1 - mov rax, r14 - shl rax, 63 - or r15, rax - shr r14, 1 - mov rax, 0xD1FFAB1E - or r14, rax - mov esi, 1 - inc r13 - test r9, r9 - jge SHORT G_M4626_IG20 - ;; size=42 bbWeight=2 PerfScore 8.50 + mov rdx, rbx + jmp G_M4626_IG19 + ;; size=8 bbWeight=1 PerfScore 2.25 G_M4626_IG15: - test r9, r9 - jge G_M4626_IG13 - ;; size=9 bbWeight=4 PerfScore 5.00 + mov rbx, rdx + ;; size=3 bbWeight=2 PerfScore 0.50 G_M4626_IG16: - mov eax, r13d - xor ecx, ecx - mov r10, bword ptr [rbp+0x10] - mov dword ptr [r10], ecx - mov dword ptr [r10+0x04], eax - mov qword ptr [r10+0x08], r14 - mov qword ptr [r10+0x10], r15 - ;; size=24 bbWeight=1 PerfScore 5.50 + mov rax, r15 + imul rax, r10 + cmp r8d, ecx + jae G_M4626_IG31 + mov edx, r8d + shl rdx, 4 + mov r13, qword ptr [r12+rdx+0x08] + mov rdx, qword ptr [r12+rdx] + mov qword ptr [rbp-0x38], rdx + mov rdx, r15 + mulx rsi, rdx, r11 + mov rdx, qword ptr [rbp-0x38] + add rdx, rax + mov qword ptr [rbp-0x38], rdx + cmp rdx, rax + setb al + movzx rax, al + dec r9 + mov rdx, rbx + mulx rbx, rdx, r10 + mov rdx, qword ptr [rbp-0x38] + add rdx, rsi + mov qword ptr [rbp-0x38], rdx + cmp rdx, rsi + setb sil + movzx rsi, sil + add rsi, rax + mov rax, rsi + mov rdx, r15 + mulx rsi, rdx, r10 + mov rdx, qword ptr [rbp-0x38] + add rdx, rbx + cmp rdx, rbx + setb r15b + movzx r15, r15b + mov ebx, r15d + add rbx, rax + mov rax, rbx + add r13, rax + cmp r13, rax + setb al + movzx rax, al + inc r8d + lea r15, [rsi+r13] + cmp r15, rsi + setb sil + movzx rsi, sil + add rsi, rax + je SHORT G_M4626_IG18 + ;; size=173 bbWeight=4 PerfScore 134.00 G_M4626_IG17: - add rsp, 88 + shr rdx, 1 + mov rax, r15 + shl rax, 63 + or rdx, rax + shr r15, 1 + mov rax, 0xD1FFAB1E + or r15, rax + mov esi, 1 + inc r14 + test r9, r9 + jge SHORT G_M4626_IG23 + ;; size=42 bbWeight=2 PerfScore 8.50 +G_M4626_IG18: + test r9, r9 + jge G_M4626_IG15 + ;; size=9 bbWeight=4 PerfScore 5.00 +G_M4626_IG19: + mov eax, r14d + xor ecx, ecx + mov rdi, bword ptr [rbp+0x10] + mov dword ptr [rdi], ecx + mov dword ptr [rdi+0x04], eax + mov qword ptr [rdi+0x08], r15 + mov qword ptr [rdi+0x10], rdx + ;; size=22 bbWeight=1 PerfScore 5.50 +G_M4626_IG20: + add rsp, 56 pop rbx pop r12 pop r13 pop r14 pop r15 pop rbp ret ;; size=15 bbWeight=1 PerfScore 4.25 -G_M4626_IG18: - test r14, r14 - je SHORT G_M4626_IG22 - ;; size=5 bbWeight=0.50 PerfScore 0.62 -G_M4626_IG19: - mov r12, bword ptr [rbp-0x78] - jmp SHORT G_M4626_IG23 - ;; size=6 bbWeight=0.25 PerfScore 0.75 -G_M4626_IG20: - jmp SHORT G_M4626_IG23 - ;; size=2 bbWeight=1 PerfScore 2.00 G_M4626_IG21: - mov bword ptr [rbp-0x78], r12 - ;; size=4 bbWeight=2 PerfScore 2.00 + test r15, r15 + je SHORT G_M4626_IG26 + ;; size=5 bbWeight=0.50 PerfScore 0.62 G_M4626_IG22: - mov rax, r15 - mul rdx:rax, r11 - cmp r8d, ecx - jae G_M4626_IG26 - mov eax, r8d - shl rax, 4 - mov r12, bword ptr [rbp-0x78] - mov r15, qword ptr [r12+rax+0x08] - mov r14d, esi - and r14d, 63 - shrx rax, qword ptr [r12+rax], r14 - mov r10d, esi - neg r10d - add r10d, 64 - shlx r10, r15, r10 - or r10, rax - shrx r14, r15, r14 - add rsi, rdi - inc r8d - dec r9 - lea r15, [r10+rdx] - cmp r15, rdx - setb r10b - movzx r10, r10b - mov eax, r10d - add r14, rax - test rsi, rsi - je G_M4626_IG12 - test r14, r14 - je SHORT G_M4626_IG21 - ;; size=111 bbWeight=4 PerfScore 76.00 + mov r12, bword ptr [rbp-0x58] + jmp G_M4626_IG27 + ;; size=9 bbWeight=0.25 PerfScore 0.75 G_M4626_IG23: - test r9, r9 - jl G_M4626_IG12 - mov r10, r14 - imul r10, r11 + mov rbx, rdx + jmp SHORT G_M4626_IG27 + ;; size=5 bbWeight=1 PerfScore 2.25 +G_M4626_IG24: + mov r11, qword ptr [rbp-0x30] + jmp G_M4626_IG13 + ;; size=9 bbWeight=0.25 PerfScore 0.75 +G_M4626_IG25: + mov bword ptr [rbp-0x58], r12 + ;; size=4 bbWeight=2 PerfScore 2.00 +G_M4626_IG26: + mov rdx, rbx + mulx r13, rdx, r10 cmp r8d, ecx - jae G_M4626_IG26 - mov eax, r8d - shl rax, 4 - mov qword ptr [rbp-0x68], rax - mov rdx, qword ptr [r12+rax+0x08] - mov eax, esi - and eax, 63 - mov dword ptr [rbp-0x6C], eax - mov rbx, qword ptr [rbp-0x68] - shrx rbx, qword ptr [r12+rbx], rax + jae G_M4626_IG31 + mov edx, r8d + shl rdx, 4 + mov r12, bword ptr [rbp-0x58] + mov rbx, qword ptr [r12+rdx+0x08] + mov r15d, esi + and r15d, 63 + shrx rdx, qword ptr [r12+rdx], r15 mov eax, esi neg eax add eax, 64 - shlx rax, rdx, rax - or rax, rbx - mov qword ptr [rbp-0x40], rax - mov ebx, dword ptr [rbp-0x6C] - shrx rdx, rdx, rbx - mov qword ptr [rbp-0x38], rdx - mov rbx, qword ptr [rbp-0x30] - mov rax, r14 - mul rdx:rax, rbx - mov qword ptr [rbp-0x48], rdx - mov rax, qword ptr [rbp-0x40] - add rax, r10 - mov qword ptr [rbp-0x40], rax - cmp rax, r10 - setb r10b - movzx r10, r10b - dec r9 - mov rax, r15 - mul rdx:rax, r11 - mov qword ptr [rbp-0x50], rdx - mov rax, qword ptr [rbp-0x40] - mov r15, qword ptr [rbp-0x48] - add rax, r15 - mov qword ptr [rbp-0x40], rax - cmp rax, r15 - setb r15b - movzx r15, r15b - add r10, r15 + shlx rax, rbx, rax + or rax, rdx + shrx r15, rbx, r15 add rsi, rdi - mov rax, r14 - mul rdx:rax, r11 - mov rax, qword ptr [rbp-0x40] - mov r14, qword ptr [rbp-0x50] - lea r15, [rax+r14] - cmp r15, r14 - setb al - movzx rax, al - add rax, r10 - mov r10, rax - add rax, qword ptr [rbp-0x38] - cmp rax, r10 - setb r10b - movzx r10, r10b inc r8d - lea r14, [rax+rdx] - cmp r14, rdx + dec r9 + lea rbx, [rax+r13] + cmp rbx, r13 setb al movzx rax, al - add rax, r10 - ;; size=238 bbWeight=0.50 PerfScore 24.00 -G_M4626_IG24: - je SHORT G_M4626_IG25 - shr r15, 1 - mov rax, r14 - shl rax, 63 - or r15, rax - shr r14, 1 - mov rax, 0xD1FFAB1E - or r14, rax - inc rsi - inc r13 - ;; size=37 bbWeight=0.50 PerfScore 2.00 -G_M4626_IG25: + mov edx, eax + add r15, rdx test rsi, rsi je G_M4626_IG12 - jmp G_M4626_IG23 - ;; size=14 bbWeight=0.50 PerfScore 1.62 -G_M4626_IG26: + test r15, r15 + je SHORT G_M4626_IG25 + ;; size=107 bbWeight=4 PerfScore 76.00 +G_M4626_IG27: + test r9, r9 + jl SHORT G_M4626_IG24 + mov rax, r15 + imul rax, r10 + cmp r8d, ecx + jae G_M4626_IG31 + mov edx, r8d + shl rdx, 4 + mov qword ptr [rbp-0x48], rdx + mov r13, qword ptr [r12+rdx+0x08] + mov edx, esi + and edx, 63 + mov dword ptr [rbp-0x4C], edx + mov r11, qword ptr [rbp-0x48] + shrx r11, qword ptr [r12+r11], rdx + mov edx, esi + neg edx + add edx, 64 + shlx rdx, r13, rdx + or rdx, r11 + mov qword ptr [rbp-0x38], rdx + mov r11d, dword ptr [rbp-0x4C] + shrx r13, r13, r11 + mov rdx, r15 + mulx rdx, r11, qword ptr [rbp-0x30] + mov qword ptr [rbp-0x40], rdx + mov r11, qword ptr [rbp-0x38] + add r11, rax + cmp r11, rax + setb al + movzx rax, al + dec r9 + mov rdx, rbx + mulx rbx, rdx, r10 + mov rdx, qword ptr [rbp-0x40] + add r11, rdx + cmp r11, rdx + setb dl + movzx rdx, dl + add rax, rdx + add rsi, rdi + mov rdx, r15 + mulx r15, rdx, r10 + add r11, rbx + cmp r11, rbx + setb dl + movzx rdx, dl + add rdx, rax + mov rax, rdx + add r13, rax + cmp r13, rax + setb al + movzx rax, al + inc r8d + lea rdx, [r15+r13] + cmp rdx, r15 + setb r13b + movzx r13, r13b + mov ebx, r13d + add rbx, rax + je SHORT G_M4626_IG29 + shr r11, 1 + mov rax, rdx + shl rax, 63 + or r11, rax + shr rdx, 1 + mov rax, 0xD1FFAB1E + or rdx, rax + inc rsi + ;; size=241 bbWeight=0.50 PerfScore 22.50 +G_M4626_IG28: + inc r14 + ;; size=3 bbWeight=0.50 PerfScore 0.12 +G_M4626_IG29: + test rsi, rsi + mov rbx, r11 + mov r15, rdx + jne G_M4626_IG27 + ;; size=15 bbWeight=0.50 PerfScore 0.88 +G_M4626_IG30: + mov r11, qword ptr [rbp-0x30] + jmp G_M4626_IG13 + ;; size=9 bbWeight=0.25 PerfScore 0.75 +G_M4626_IG31: call CORINFO_HELP_RNGCHKFAIL int3 ;; size=6 bbWeight=0 PerfScore 0.00 -; Total bytes of code 953, prolog size 22, PerfScore 415.00, instruction count 270, allocated bytes for code 953 (MethodHash=2d59eded) for method System.Number:DiyFp128EvaluatePositivePolynomial(byref,long,System.ReadOnlySpan`1[System.Number+DiyFp128FixedCoefficient],int,long,byref) (FullOpts) +; Total bytes of code 932, prolog size 19, PerfScore 390.62, instruction count 266, allocated bytes for code 935 (MethodHash=2d59eded) for method System.Number:DiyFp128EvaluatePositivePolynomial(byref,long,System.ReadOnlySpan`1[System.Number+DiyFp128FixedCoefficient],int,long,byref) (FullOpts) ; ============================================================ ```
-16 (-5.10 % of base) - System.Number:DiyFp128ReduceBuildInteger(System.UInt128,int,System.Span`1[ulong]):int ```diff ; Assembly listing for method System.Number:DiyFp128ReduceBuildInteger(System.UInt128,int,System.Span`1[ulong]):int (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rbp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 24 single block inlinees; 5 inlinees without PGO data ; Final local variable assignments ; ;* V00 arg0 [V00 ] ( 0, 0 ) struct (16) zero-ref multireg-arg single-def ; V01 arg1 [V01,T19] ( 3, 3 ) int -> rdx single-def ;* V02 arg2 [V02 ] ( 0, 0 ) struct (16) zero-ref multireg-arg ld-addr-op single-def -; V03 loc0 [V03,T16] ( 9, 14.66) int -> [rbp-0x1C] +; V03 loc0 [V03,T16] ( 9, 14.66) int -> registers ;* V04 loc1 [V04 ] ( 0, 0 ) long -> zero-ref -; V05 loc2 [V05,T06] ( 7, 32 ) int -> [rbp-0x20] +; V05 loc2 [V05,T06] ( 7, 32 ) int -> [rbp-0x24] ; V06 loc3 [V06,T14] ( 3, 16 ) int -> rdi ; V07 loc4 [V07,T11] ( 3, 20 ) long -> rsi ;* V08 loc5 [V08 ] ( 0, 0 ) struct (16) zero-ref ;* V09 loc6 [V09 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ; V10 loc7 [V10,T20] ( 7, 4.96) int -> r11 ;* V11 loc8 [V11 ] ( 0, 0 ) struct (16) zero-ref ;# V12 OutArgs [V12 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ;* V13 tmp1 [V13 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V14 tmp2 [V14 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V15 tmp3 [V15 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V16 tmp4 [V16 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V17 tmp5 [V17 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V18 tmp6 [V18 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V19 tmp7 [V19 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ; V20 tmp8 [V20,T13] ( 4, 16 ) int -> rax "impSpillLclRefs" ;* V21 tmp9 [V21 ] ( 0, 0 ) byref -> zero-ref "impAppendStmt" ;* V22 tmp10 [V22 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V23 tmp11 [V23 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V24 tmp12 [V24 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V25 tmp13 [V25 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V26 tmp14 [V26 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V27 tmp15 [V27 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V28 tmp16 [V28 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V29 tmp17 [V29,T18] ( 3, 8 ) int -> rdi "Inline return value spill temp" ;* V30 tmp18 [V30 ] ( 0, 0 ) struct (16) zero-ref "ReadOnlySpan for CreateSpan" ;* V31 tmp19 [V31 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V32 tmp20 [V32 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V33 tmp21 [V33 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V34 tmp22 [V34 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V35 tmp23 [V35 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V36 tmp24 [V36 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V37 tmp25 [V37 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V38 tmp26 [V38 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V39 tmp27 [V39 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V40 tmp28 [V40 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V41 tmp29 [V41 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V42 tmp30 [V42 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V43 tmp31 [V43 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V44 tmp32 [V44,T02] ( 6, 48 ) long -> r9 "Inline stloc first use temp" -; V45 tmp33 [V45,T07] ( 4, 32 ) long -> r14 "Inline stloc first use temp" +; V45 tmp33 [V45,T07] ( 4, 32 ) long -> r13 "Inline stloc first use temp" ;* V46 tmp34 [V46 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V47 tmp35 [V47 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V48 tmp36 [V48 ] ( 0, 0 ) struct (16) zero-ref "Inline return value spill temp" ;* V49 tmp37 [V49 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ;* V50 tmp38 [V50 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V51 tmp39 [V51 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V52 tmp40 [V52 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V53 tmp41 [V53 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V54 tmp42 [V54 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V55 tmp43 [V55 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V56 tmp44 [V56,T22] ( 0, 0 ) ubyte -> zero-ref "Inline return value spill temp" ; V57 tmp45 [V57,T23] ( 2, 2 ) long -> rdi single-def "field V00._lower (fldOffset=0x0)" P-INDEP ; V58 tmp46 [V58,T21] ( 3, 2.50) long -> rsi single-def "field V00._upper (fldOffset=0x8)" P-INDEP ; V59 tmp47 [V59,T05] ( 8, 36.50) byref -> rcx single-def "field V02._reference (fldOffset=0x0)" P-INDEP ; V60 tmp48 [V60,T17] ( 6, 6.66) int -> r8 single-def "field V02._length (fldOffset=0x8)" P-INDEP ; V61 tmp49 [V61,T04] ( 7, 42 ) long -> r9 "field V08._lower (fldOffset=0x0)" P-INDEP ; V62 tmp50 [V62,T12] ( 3, 20 ) long -> r10 "field V08._upper (fldOffset=0x8)" P-INDEP ;* V63 tmp51 [V63 ] ( 0, 0 ) byref -> zero-ref "field V09._reference (fldOffset=0x0)" P-INDEP ;* V64 tmp52 [V64 ] ( 0, 0 ) int -> zero-ref "field V09._length (fldOffset=0x8)" P-INDEP ;* V65 tmp53 [V65 ] ( 0, 0 ) long -> zero-ref "field V11._lower (fldOffset=0x0)" P-INDEP ;* V66 tmp54 [V66 ] ( 0, 0 ) long -> zero-ref "field V11._upper (fldOffset=0x8)" P-INDEP ;* V67 tmp55 [V67 ] ( 0, 0 ) long -> zero-ref "field V14._lower (fldOffset=0x0)" P-INDEP ;* V68 tmp56 [V68 ] ( 0, 0 ) long -> zero-ref "field V14._upper (fldOffset=0x8)" P-INDEP ;* V69 tmp57 [V69 ] ( 0, 0 ) long -> zero-ref "field V15._lower (fldOffset=0x0)" P-INDEP ;* V70 tmp58 [V70 ] ( 0, 0 ) long -> zero-ref "field V15._upper (fldOffset=0x8)" P-INDEP ;* V71 tmp59 [V71 ] ( 0, 0 ) long -> zero-ref "field V16._lower (fldOffset=0x0)" P-INDEP ;* V72 tmp60 [V72 ] ( 0, 0 ) long -> zero-ref "field V16._upper (fldOffset=0x8)" P-INDEP ;* V73 tmp61 [V73 ] ( 0, 0 ) long -> zero-ref "field V17._lower (fldOffset=0x0)" P-INDEP ;* V74 tmp62 [V74 ] ( 0, 0 ) long -> zero-ref "field V17._upper (fldOffset=0x8)" P-INDEP ;* V75 tmp63 [V75 ] ( 0, 0 ) long -> zero-ref "field V19._lower (fldOffset=0x0)" P-INDEP ;* V76 tmp64 [V76 ] ( 0, 0 ) long -> zero-ref "field V19._upper (fldOffset=0x8)" P-INDEP ;* V77 tmp65 [V77 ] ( 0, 0 ) long -> zero-ref "field V22._lower (fldOffset=0x0)" P-INDEP ;* V78 tmp66 [V78 ] ( 0, 0 ) long -> zero-ref "field V22._upper (fldOffset=0x8)" P-INDEP ;* V79 tmp67 [V79 ] ( 0, 0 ) long -> zero-ref "field V25._lower (fldOffset=0x0)" P-INDEP ;* V80 tmp68 [V80 ] ( 0, 0 ) long -> zero-ref "field V25._upper (fldOffset=0x8)" P-INDEP ;* V81 tmp69 [V81 ] ( 0, 0 ) long -> zero-ref "field V27._lower (fldOffset=0x0)" P-INDEP ;* V82 tmp70 [V82 ] ( 0, 0 ) long -> zero-ref "field V27._upper (fldOffset=0x8)" P-INDEP ;* V83 tmp71 [V83 ] ( 0, 0 ) byref -> zero-ref "field V30._reference (fldOffset=0x0)" P-INDEP ;* V84 tmp72 [V84 ] ( 0, 0 ) int -> zero-ref "field V30._length (fldOffset=0x8)" P-INDEP ;* V85 tmp73 [V85 ] ( 0, 0 ) long -> zero-ref "field V31._lower (fldOffset=0x0)" P-INDEP ;* V86 tmp74 [V86 ] ( 0, 0 ) long -> zero-ref "field V31._upper (fldOffset=0x8)" P-INDEP ; V87 tmp75 [V87,T08] ( 4, 32 ) long -> r15 "field V33._lower (fldOffset=0x0)" P-INDEP ;* V88 tmp76 [V88 ] ( 0, 0 ) long -> zero-ref "field V33._upper (fldOffset=0x8)" P-INDEP ;* V89 tmp77 [V89 ] ( 0, 0 ) long -> zero-ref "field V34._lower (fldOffset=0x0)" P-INDEP ;* V90 tmp78 [V90 ] ( 0, 0 ) long -> zero-ref "field V34._upper (fldOffset=0x8)" P-INDEP ;* V91 tmp79 [V91 ] ( 0, 0 ) long -> zero-ref "field V36._lower (fldOffset=0x0)" P-INDEP ;* V92 tmp80 [V92 ] ( 0, 0 ) long -> zero-ref "field V36._upper (fldOffset=0x8)" P-INDEP ;* V93 tmp81 [V93 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V40.Item1 (fldOffset=0x0)" P-DEP ;* V94 tmp82 [V94 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V40.Item2 (fldOffset=0x8)" P-DEP -; V95 tmp83 [V95,T03] ( 6, 48 ) long -> rax "field V41.Item1 (fldOffset=0x0)" P-INDEP -; V96 tmp84 [V96,T09] ( 4, 32 ) long -> rdx "field V41.Item2 (fldOffset=0x8)" P-INDEP +; V95 tmp83 [V95,T03] ( 6, 48 ) long -> r15 "field V41.Item1 (fldOffset=0x0)" P-INDEP +; V96 tmp84 [V96,T09] ( 4, 32 ) long -> r14 "field V41.Item2 (fldOffset=0x8)" P-INDEP ;* V97 tmp85 [V97 ] ( 0, 0 ) long -> zero-ref "field V46._lower (fldOffset=0x0)" P-INDEP -; V98 tmp86 [V98,T10] ( 4, 32 ) long -> rdx "field V46._upper (fldOffset=0x8)" P-INDEP +; V98 tmp86 [V98,T10] ( 4, 32 ) long -> r14 "field V46._upper (fldOffset=0x8)" P-INDEP ;* V99 tmp87 [V99 ] ( 0, 0 ) long -> zero-ref "field V48._lower (fldOffset=0x0)" P-INDEP ;* V100 tmp88 [V100 ] ( 0, 0 ) long -> zero-ref "field V48._upper (fldOffset=0x8)" P-INDEP ;* V101 tmp89 [V101 ] ( 0, 0 ) long -> zero-ref "field V51._lower (fldOffset=0x0)" P-INDEP ;* V102 tmp90 [V102 ] ( 0, 0 ) long -> zero-ref "field V51._upper (fldOffset=0x8)" P-INDEP ;* V103 tmp91 [V103 ] ( 0, 0 ) long -> zero-ref "field V53._lower (fldOffset=0x0)" P-INDEP ;* V104 tmp92 [V104 ] ( 0, 0 ) long -> zero-ref "field V53._upper (fldOffset=0x8)" P-INDEP ;* V105 tmp93 [V105 ] ( 0, 0 ) long -> zero-ref "field V55._lower (fldOffset=0x0)" P-INDEP ;* V106 tmp94 [V106 ] ( 0, 0 ) long -> zero-ref "field V55._upper (fldOffset=0x8)" P-INDEP ;* V107 cse0 [V107,T15] ( 0, 0 ) long -> zero-ref "CSE #01: aggressive" ; V108 rat0 [V108,T00] ( 5, 65.36) long -> r11 "Strength reduced derived IV" ; V109 rat1 [V109,T01] ( 4, 49.52) int -> rbx "Trip count IV" ; -; Lcl frame size = 8 +; Lcl frame size = 16 G_M12515_IG01: push rbp push r15 push r14 + push r13 push rbx - push rax - lea rbp, [rsp+0x20] - ;; size=12 bbWeight=1 PerfScore 5.50 + sub rsp, 16 + lea rbp, [rsp+0x30] + ;; size=17 bbWeight=1 PerfScore 5.75 G_M12515_IG02: test r8d, r8d - je G_M12515_IG21 + je G_M12515_IG18 mov qword ptr [rcx], rdi mov eax, 1 test rsi, rsi je SHORT G_M12515_IG04 ;; size=22 bbWeight=1 PerfScore 3.75 G_M12515_IG03: cmp r8d, 1 - jbe G_M12515_IG21 + jbe G_M12515_IG18 mov qword ptr [rcx+0x08], rsi mov eax, 2 ;; size=19 bbWeight=0.50 PerfScore 1.25 G_M12515_IG04: test edx, edx - jg SHORT G_M12515_IG07 - ;; size=4 bbWeight=1 PerfScore 1.25 + jle G_M12515_IG15 + ;; size=8 bbWeight=1 PerfScore 1.25 G_M12515_IG05: - mov dword ptr [rbp-0x1C], eax - jmp G_M12515_IG17 - align [0 bytes for IG13] - ;; size=8 bbWeight=0.50 PerfScore 1.50 -G_M12515_IG06: - mov eax, dword ptr [rbp-0x1C] - ;; size=3 bbWeight=4 PerfScore 4.00 -G_M12515_IG07: cmp edx, 19 - jg SHORT G_M12515_IG09 + jg SHORT G_M12515_IG07 ;; size=5 bbWeight=4 PerfScore 5.00 -G_M12515_IG08: - mov dword ptr [rbp-0x20], edx +G_M12515_IG06: + mov dword ptr [rbp-0x24], edx mov edi, edx - mov edx, dword ptr [rbp-0x20] - jmp SHORT G_M12515_IG10 + mov edx, dword ptr [rbp-0x24] + jmp SHORT G_M12515_IG08 + align [0 bytes for IG11] ;; size=10 bbWeight=2 PerfScore 8.50 -G_M12515_IG09: +G_M12515_IG07: mov edi, 19 ;; size=5 bbWeight=2 PerfScore 0.50 -G_M12515_IG10: +G_M12515_IG08: mov esi, edi mov r9, 0xD1FFAB1E ; static handle mov rsi, qword ptr [r9+8*rsi] xor r9d, r9d xor r10d, r10d xor r11d, r11d test eax, eax - jg SHORT G_M12515_IG12 + jg SHORT G_M12515_IG10 ;; size=29 bbWeight=4 PerfScore 18.00 -G_M12515_IG11: - mov dword ptr [rbp-0x20], edx - mov dword ptr [rbp-0x1C], eax - jmp SHORT G_M12515_IG14 - ;; size=8 bbWeight=2 PerfScore 8.00 -G_M12515_IG12: +G_M12515_IG09: + mov dword ptr [rbp-0x24], edx + jmp SHORT G_M12515_IG12 + ;; size=5 bbWeight=2 PerfScore 6.00 +G_M12515_IG10: cmp eax, r8d - jg SHORT G_M12515_IG19 + jg SHORT G_M12515_IG16 xor r11d, r11d - mov dword ptr [rbp-0x1C], eax mov ebx, eax - mov dword ptr [rbp-0x20], edx - ;; size=16 bbWeight=2 PerfScore 7.50 -G_M12515_IG13: + mov dword ptr [rbp-0x24], edx + ;; size=13 bbWeight=2 PerfScore 5.50 +G_M12515_IG11: mov r15, qword ptr [rcx+r11] - mov rax, rsi - mul rdx:rax, r15 - add r9, rax - cmp r9, rax - setb al - movzx rax, al - mov r14d, eax - add rdx, r10 - add rdx, r14 + mov rdx, rsi + mulx r14, r15, r15 + add r9, r15 + cmp r9, r15 + setb dl + movzx rdx, dl + mov r13d, edx + add r14, r10 + add r14, r13 mov qword ptr [rcx+r11], r9 - mov r9, rdx + mov r9, r14 add r11, 8 dec ebx - jne SHORT G_M12515_IG13 - ;; size=46 bbWeight=15.84 PerfScore 158.40 -G_M12515_IG14: + jne SHORT G_M12515_IG11 + ;; size=48 bbWeight=15.84 PerfScore 158.40 +G_M12515_IG12: test r9, r9 - je SHORT G_M12515_IG16 + je SHORT G_M12515_IG14 ;; size=5 bbWeight=4 PerfScore 5.00 -G_M12515_IG15: - mov eax, dword ptr [rbp-0x1C] +G_M12515_IG13: lea edx, [rax+0x01] cmp eax, r8d - jae SHORT G_M12515_IG21 + jae SHORT G_M12515_IG18 + mov eax, eax mov qword ptr [rcx+8*rax], r9 - mov dword ptr [rbp-0x1C], edx - ;; size=18 bbWeight=2 PerfScore 9.50 -G_M12515_IG16: - mov edx, dword ptr [rbp-0x20] + mov eax, edx + ;; size=16 bbWeight=2 PerfScore 6.50 +G_M12515_IG14: + mov edx, dword ptr [rbp-0x24] sub edx, edi test edx, edx - jg G_M12515_IG06 + jg G_M12515_IG05 ;; size=13 bbWeight=8 PerfScore 20.00 -G_M12515_IG17: - mov eax, dword ptr [rbp-0x1C] - ;; size=3 bbWeight=1 PerfScore 1.00 -G_M12515_IG18: - add rsp, 8 +G_M12515_IG15: + add rsp, 16 pop rbx + pop r13 pop r14 pop r15 pop rbp ret - ;; size=11 bbWeight=1 PerfScore 3.25 -G_M12515_IG19: - mov dword ptr [rbp-0x20], edx - mov dword ptr [rbp-0x1C], eax - ;; size=6 bbWeight=0.01 PerfScore 0.02 -G_M12515_IG20: + ;; size=13 bbWeight=1 PerfScore 3.75 +G_M12515_IG16: + mov dword ptr [rbp-0x24], edx + ;; size=3 bbWeight=0.01 PerfScore 0.01 +G_M12515_IG17: cmp r11d, r8d - jae SHORT G_M12515_IG21 + jae SHORT G_M12515_IG18 mov r15d, r11d mov r15, qword ptr [rcx+8*r15] - mov rax, rsi - mul rdx:rax, r15 - add r9, rax - cmp r9, rax - setb al - movzx rax, al - mov r14d, eax - add rdx, r10 - add rdx, r14 - mov eax, r11d - mov qword ptr [rcx+8*rax], r9 - mov r9, rdx + mov rdx, rsi + mulx r14, r15, r15 + add r9, r15 + cmp r9, r15 + setb dl + movzx rdx, dl + mov r13d, edx + add r14, r10 + add r14, r13 + mov edx, r11d + mov qword ptr [rcx+8*rdx], r9 + mov r9, r14 inc r11d - mov eax, dword ptr [rbp-0x1C] cmp r11d, eax - mov dword ptr [rbp-0x1C], eax - jl SHORT G_M12515_IG20 - jmp SHORT G_M12515_IG14 - ;; size=65 bbWeight=0.16 PerfScore 2.52 -G_M12515_IG21: + jl SHORT G_M12515_IG17 + jmp SHORT G_M12515_IG12 + ;; size=61 bbWeight=0.16 PerfScore 2.20 +G_M12515_IG18: call CORINFO_HELP_RNGCHKFAIL int3 ;; size=6 bbWeight=0 PerfScore 0.00 -; Total bytes of code 314, prolog size 12, PerfScore 264.44, instruction count 106, allocated bytes for code 314 (MethodHash=a387cf1c) for method System.Number:DiyFp128ReduceBuildInteger(System.UInt128,int,System.Span`1[ulong]):int (FullOpts) +; Total bytes of code 298, prolog size 17, PerfScore 251.36, instruction count 99, allocated bytes for code 298 (MethodHash=a387cf1c) for method System.Number:DiyFp128ReduceBuildInteger(System.UInt128,int,System.Span`1[ulong]):int (FullOpts) ; ============================================================ ```
-15 (-9.43 % of base) - System.Decimal+DecCalc:Div128By96(byref,byref):uint ```diff ; Assembly listing for method System.Decimal+DecCalc:Div128By96(byref,byref):uint (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rbp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 8 single block inlinees; 2 inlinees without PGO data ; Final local variable assignments ; ; V00 arg0 [V00,T06] ( 6, 4.50) byref -> rdi single-def ; V01 arg1 [V01,T07] ( 4, 3.50) byref -> rsi single-def ; V02 loc0 [V02,T08] ( 4, 3 ) long -> rax ; V03 loc1 [V03,T02] ( 6, 12.50) int -> rcx -; V04 loc2 [V04,T04] ( 5, 9.50) int -> [rbp-0x04] -; V05 loc3 [V05,T00] ( 11, 19 ) int -> r9 +; V04 loc2 [V04,T04] ( 5, 9.50) int -> rax +; V05 loc3 [V05,T00] ( 11, 19 ) int -> r10 ; V06 loc4 [V06,T05] ( 3, 8.50) long -> rsi ld-addr-op -; V07 loc5 [V07,T09] ( 4, 2 ) int -> rdx -; V08 loc6 [V08,T01] ( 6, 13.50) long -> r8 +; V07 loc5 [V07,T09] ( 4, 2 ) int -> r8 +; V08 loc6 [V08,T01] ( 6, 13.50) long -> r9 ;# V09 OutArgs [V09 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ;* V10 tmp1 [V10 ] ( 0, 0 ) struct ( 8) zero-ref multireg-ret multireg-dest "dup spill" ; V11 tmp2 [V11,T03] ( 3, 12 ) int -> rdx "impSpillLclRefs" ;* V12 tmp3 [V12 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ;* V13 tmp4 [V13 ] ( 0, 0 ) struct ( 8) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Inline return value spill temp" ;* V14 tmp5 [V14 ] ( 0, 0 ) struct ( 8) zero-ref do-not-enreg[SRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V15 tmp6 [V15 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V16 tmp7 [V16 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V17 tmp8 [V17 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V18 tmp9 [V18 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V19 tmp10 [V19 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V20 tmp11 [V20 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ;* V21 tmp12 [V21 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ; V22 tmp13 [V22,T12] ( 2, 1 ) int -> rax "field V10.Item1 (fldOffset=0x0)" P-INDEP -; V23 tmp14 [V23,T13] ( 2, 1 ) int -> [rbp-0x08] spill-single-def "field V10.Item2 (fldOffset=0x4)" P-INDEP +; V23 tmp14 [V23,T13] ( 2, 1 ) int -> [rbp-0x04] spill-single-def "field V10.Item2 (fldOffset=0x4)" P-INDEP ;* V24 tmp15 [V24 ] ( 0, 0 ) int -> zero-ref do-not-enreg[] "field V13.Item1 (fldOffset=0x0)" P-DEP ;* V25 tmp16 [V25 ] ( 0, 0 ) int -> zero-ref do-not-enreg[] "field V13.Item2 (fldOffset=0x4)" P-DEP ;* V26 tmp17 [V26 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V18.Item1 (fldOffset=0x0)" P-DEP ;* V27 tmp18 [V27 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V18.Item2 (fldOffset=0x8)" P-DEP -; V28 tmp19 [V28,T10] ( 3, 1.50) long -> rax "field V19.Item1 (fldOffset=0x0)" P-INDEP -; V29 tmp20 [V29,T14] ( 2, 1 ) long -> rdx "field V19.Item2 (fldOffset=0x8)" P-INDEP +; V28 tmp19 [V28,T10] ( 3, 1.50) long -> rdx "field V19.Item1 (fldOffset=0x0)" P-INDEP +; V29 tmp20 [V29,T14] ( 2, 1 ) long -> r8 "field V19.Item2 (fldOffset=0x8)" P-INDEP ; V30 cse0 [V30,T11] ( 3, 1.50) long -> rsi "CSE #02: moderate" ; ; Lcl frame size = 16 G_M25057_IG01: push rbp sub rsp, 16 lea rbp, [rsp+0x10] ;; size=10 bbWeight=1 PerfScore 1.75 G_M25057_IG02: mov rax, qword ptr [rdi+0x08] mov ecx, dword ptr [rsi+0x08] mov edx, ecx cmp rax, rdx - jb SHORT G_M25057_IG13 + jb SHORT G_M25057_IG11 ;; size=14 bbWeight=1 PerfScore 5.50 G_M25057_IG03: mov rdx, rax shr rdx, 32 div edx:eax, ecx - mov dword ptr [rbp-0x08], edx + mov dword ptr [rbp-0x04], edx mov rsi, qword ptr [rsi] - mov dword ptr [rbp-0x04], eax mov r8d, eax - mov rax, r8 - mul rdx:rax, rsi - mov r8, qword ptr [rdi] - sub r8, rax - mov r9d, dword ptr [rbp-0x08] - sub r9d, edx - not rax - cmp rax, r8 - jb SHORT G_M25057_IG05 - not edx - cmp edx, r9d - jb SHORT G_M25057_IG06 - ;; size=55 bbWeight=0.50 PerfScore 19.88 + mov rdx, r8 + mulx r8, rdx, rsi + mov r9, qword ptr [rdi] + sub r9, rdx + mov r10d, dword ptr [rbp-0x04] + sub r10d, r8d + not rdx + cmp rdx, r9 + jb SHORT G_M25057_IG04 + not r8d + cmp r8d, r10d + jae SHORT G_M25057_IG09 + jmp SHORT G_M25057_IG05 + ;; size=57 bbWeight=0.50 PerfScore 20.38 G_M25057_IG04: - mov eax, dword ptr [rbp-0x04] - jmp SHORT G_M25057_IG11 - align [0 bytes for IG07] - ;; size=5 bbWeight=0.25 PerfScore 0.75 + dec r10d + mov edx, r8d + not edx + cmp edx, r10d + ja SHORT G_M25057_IG09 + ;; size=13 bbWeight=0.50 PerfScore 1.00 G_M25057_IG05: - dec r9d - mov eax, edx - not eax - cmp eax, r9d - ja SHORT G_M25057_IG15 - ;; size=12 bbWeight=0.50 PerfScore 1.00 + align [0 bytes for IG06] + ;; size=0 bbWeight=0.50 PerfScore 0.00 G_M25057_IG06: - jmp SHORT G_M25057_IG09 - ;; size=2 bbWeight=0.50 PerfScore 1.00 -G_M25057_IG07: - cmp r9d, ecx - jb SHORT G_M25057_IG11 - ;; size=5 bbWeight=4 PerfScore 5.00 -G_M25057_IG08: - mov dword ptr [rbp-0x04], eax - ;; size=3 bbWeight=2 PerfScore 2.00 -G_M25057_IG09: - mov eax, dword ptr [rbp-0x04] dec eax - add r8, rsi - add r9d, ecx - cmp r8, rsi - jae SHORT G_M25057_IG07 - ;; size=16 bbWeight=4 PerfScore 12.00 -G_M25057_IG10: - mov edx, r9d - lea r9d, [rdx+0x01] + add r9, rsi + add r10d, ecx + cmp r9, rsi + jae SHORT G_M25057_IG08 + ;; size=13 bbWeight=4 PerfScore 8.00 +G_M25057_IG07: + mov edx, r10d + lea r10d, [rdx+0x01] cmp edx, ecx - jae SHORT G_M25057_IG07 + jb SHORT G_M25057_IG09 ;; size=11 bbWeight=2 PerfScore 4.00 -G_M25057_IG11: - mov qword ptr [rdi], r8 - mov dword ptr [rdi+0x08], r9d +G_M25057_IG08: + cmp r10d, ecx + jae SHORT G_M25057_IG06 + ;; size=5 bbWeight=4 PerfScore 5.00 +G_M25057_IG09: + mov qword ptr [rdi], r9 + mov dword ptr [rdi+0x08], r10d ;; size=7 bbWeight=0.50 PerfScore 1.00 +G_M25057_IG10: + add rsp, 16 + pop rbp + ret + ;; size=6 bbWeight=0.50 PerfScore 0.88 +G_M25057_IG11: + xor eax, eax + ;; size=2 bbWeight=0.50 PerfScore 0.12 G_M25057_IG12: add rsp, 16 pop rbp ret ;; size=6 bbWeight=0.50 PerfScore 0.88 -G_M25057_IG13: - xor eax, eax - ;; size=2 bbWeight=0.50 PerfScore 0.12 -G_M25057_IG14: - add rsp, 16 - pop rbp - ret - ;; size=6 bbWeight=0.50 PerfScore 0.88 -G_M25057_IG15: - mov eax, dword ptr [rbp-0x04] - jmp SHORT G_M25057_IG11 - ;; size=5 bbWeight=0.25 PerfScore 0.75 -; Total bytes of code 159, prolog size 10, PerfScore 56.50, instruction count 60, allocated bytes for code 163 (MethodHash=8d9d9e1e) for method System.Decimal+DecCalc:Div128By96(byref,byref):uint (FullOpts) +; Total bytes of code 144, prolog size 10, PerfScore 48.50, instruction count 53, allocated bytes for code 148 (MethodHash=8d9d9e1e) for method System.Decimal+DecCalc:Div128By96(byref,byref):uint (FullOpts) ; ============================================================ ```
-15 (-2.52 % of base) - System.Numerics.BigIntegerCalculator:PowCore(nuint,System.ReadOnlySpan`1[nuint],nuint,nuint):nuint ```diff ; Assembly listing for method System.Numerics.BigIntegerCalculator:PowCore(nuint,System.ReadOnlySpan`1[nuint],nuint,nuint):nuint (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rbp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 23 single block inlinees; 2 inlinees without PGO data ; Final local variable assignments ; ; V00 arg0 [V00,T02] ( 19, 67 ) long -> rbx ;* V01 arg1 [V01 ] ( 0, 0 ) struct (16) zero-ref multireg-arg ld-addr-op single-def ; V02 arg2 [V02,T03] ( 12, 36 ) long -> r15 single-def ; V03 arg3 [V03,T04] ( 11, 35 ) long -> r14 ; V04 loc0 [V04,T05] ( 3, 33 ) ubyte -> [rbp-0x2C] spill-single-def ;* V05 loc1 [V05,T21] ( 0, 0 ) int -> zero-ref ; V06 loc2 [V06,T01] ( 10, 84 ) long -> [rbp-0x38] ;* V07 loc3 [V07,T19] ( 0, 0 ) int -> zero-ref ;# V08 OutArgs [V08 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ;* V09 tmp1 [V09 ] ( 0, 0 ) int -> zero-ref ;* V10 tmp2 [V10 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V11 tmp3 [V11 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V12 tmp4 [V12 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V13 tmp5 [V13 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V14 tmp6 [V14 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V15 tmp7 [V15 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V16 tmp8 [V16 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V17 tmp9 [V17 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V18 tmp10 [V18 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V19 tmp11 [V19 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ; V20 tmp12 [V20,T18] ( 3, 6 ) int -> rsi "Span.get_Item index" ;* V21 tmp13 [V21 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V22 tmp14 [V22 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V23 tmp15 [V23 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V24 tmp16 [V24 ] ( 0, 0 ) struct (16) zero-ref multireg-arg ld-addr-op "NewObj constructor temp" ;* V25 tmp17 [V25 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V26 tmp18 [V26 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V27 tmp19 [V27 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V28 tmp20 [V28 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V29 tmp21 [V29 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V30 tmp22 [V30 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V31 tmp23 [V31 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V32 tmp24 [V32 ] ( 0, 0 ) struct (16) zero-ref multireg-arg ld-addr-op "NewObj constructor temp" ; V33 tmp25 [V33,T06] ( 4, 32 ) struct (32) [rbp-0x58] do-not-enreg[DAS] defined-via-address "location for address-of(RValue)" ;* V34 tmp26 [V34 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V35 tmp27 [V35 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V36 tmp28 [V36 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V37 tmp29 [V37 ] ( 0, 0 ) struct (16) zero-ref multireg-arg ld-addr-op "NewObj constructor temp" ;* V38 tmp30 [V38 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V39 tmp31 [V39 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V40 tmp32 [V40 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V41 tmp33 [V41 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V42 tmp34 [V42 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V43 tmp35 [V43 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V44 tmp36 [V44 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V45 tmp37 [V45 ] ( 0, 0 ) struct (16) zero-ref multireg-arg ld-addr-op "NewObj constructor temp" ; V46 tmp38 [V46,T07] ( 4, 32 ) struct (32) [rbp-0x78] do-not-enreg[DAS] defined-via-address "location for address-of(RValue)" ; V47 tmp39 [V47,T16] ( 4, 6 ) byref -> r13 single-def "field V01._reference (fldOffset=0x0)" P-INDEP ; V48 tmp40 [V48,T17] ( 8, 5.50) int -> r12 single-def "field V01._length (fldOffset=0x8)" P-INDEP ;* V49 tmp41 [V49 ] ( 0, 0 ) long -> zero-ref "field V10._lower (fldOffset=0x0)" P-INDEP ;* V50 tmp42 [V50 ] ( 0, 0 ) long -> zero-ref "field V10._upper (fldOffset=0x8)" P-INDEP ;* V51 tmp43 [V51 ] ( 0, 0 ) long -> zero-ref "field V11._lower (fldOffset=0x0)" P-INDEP ;* V52 tmp44 [V52 ] ( 0, 0 ) long -> zero-ref "field V11._upper (fldOffset=0x8)" P-INDEP ;* V53 tmp45 [V53 ] ( 0, 0 ) long -> zero-ref "field V12._lower (fldOffset=0x0)" P-INDEP ;* V54 tmp46 [V54 ] ( 0, 0 ) long -> zero-ref "field V12._upper (fldOffset=0x8)" P-INDEP ;* V55 tmp47 [V55 ] ( 0, 0 ) long -> zero-ref "field V13._lower (fldOffset=0x0)" P-INDEP ;* V56 tmp48 [V56 ] ( 0, 0 ) long -> zero-ref "field V13._upper (fldOffset=0x8)" P-INDEP ; V57 tmp49 [V57,T08] ( 4, 16 ) long -> rbx "field V14._lower (fldOffset=0x0)" P-INDEP ;* V58 tmp50 [V58 ] ( 0, 0 ) long -> zero-ref "field V14._upper (fldOffset=0x8)" P-INDEP ;* V59 tmp51 [V59 ] ( 0, 0 ) long -> zero-ref "field V15._lower (fldOffset=0x0)" P-INDEP ;* V60 tmp52 [V60 ] ( 0, 0 ) long -> zero-ref "field V15._upper (fldOffset=0x8)" P-INDEP ;* V61 tmp53 [V61 ] ( 0, 0 ) long -> zero-ref "field V16._lower (fldOffset=0x0)" P-INDEP ;* V62 tmp54 [V62 ] ( 0, 0 ) long -> zero-ref "field V16._upper (fldOffset=0x8)" P-INDEP ;* V63 tmp55 [V63 ] ( 0, 0 ) long -> zero-ref "field V17._lower (fldOffset=0x0)" P-INDEP ;* V64 tmp56 [V64 ] ( 0, 0 ) long -> zero-ref "field V17._upper (fldOffset=0x8)" P-INDEP ;* V65 tmp57 [V65 ] ( 0, 0 ) long -> zero-ref "field V18._lower (fldOffset=0x0)" P-INDEP ;* V66 tmp58 [V66 ] ( 0, 0 ) long -> zero-ref "field V18._upper (fldOffset=0x8)" P-INDEP ; V67 tmp59 [V67,T09] ( 4, 16 ) long -> r14 "field V19._lower (fldOffset=0x0)" P-INDEP ;* V68 tmp60 [V68 ] ( 0, 0 ) long -> zero-ref "field V19._upper (fldOffset=0x8)" P-INDEP ;* V69 tmp61 [V69 ] ( 0, 0 ) long -> zero-ref "field V21._lower (fldOffset=0x0)" P-INDEP ;* V70 tmp62 [V70 ] ( 0, 0 ) long -> zero-ref "field V21._upper (fldOffset=0x8)" P-INDEP ;* V71 tmp63 [V71 ] ( 0, 0 ) long -> zero-ref "field V22._lower (fldOffset=0x0)" P-INDEP ;* V72 tmp64 [V72 ] ( 0, 0 ) long -> zero-ref "field V22._upper (fldOffset=0x8)" P-INDEP ;* V73 tmp65 [V73 ] ( 0, 0 ) long -> zero-ref "field V24._lower (fldOffset=0x0)" P-INDEP ;* V74 tmp66 [V74 ] ( 0, 0 ) long -> zero-ref "field V24._upper (fldOffset=0x8)" P-INDEP ;* V75 tmp67 [V75 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V28.Item1 (fldOffset=0x0)" P-DEP ;* V76 tmp68 [V76 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V28.Item2 (fldOffset=0x8)" P-DEP -; V77 tmp69 [V77,T10] ( 4, 16 ) long -> rax "field V29.Item1 (fldOffset=0x0)" P-INDEP +; V77 tmp69 [V77,T10] ( 4, 16 ) long -> rsi "field V29.Item1 (fldOffset=0x0)" P-INDEP ; V78 tmp70 [V78,T11] ( 4, 16 ) long -> rdx "field V29.Item2 (fldOffset=0x8)" P-INDEP ;* V79 tmp71 [V79 ] ( 0, 0 ) long -> zero-ref "field V32._lower (fldOffset=0x0)" P-INDEP ;* V80 tmp72 [V80 ] ( 0, 0 ) long -> zero-ref "field V32._upper (fldOffset=0x8)" P-INDEP ;* V81 tmp73 [V81 ] ( 0, 0 ) long -> zero-ref "field V34._lower (fldOffset=0x0)" P-INDEP ;* V82 tmp74 [V82 ] ( 0, 0 ) long -> zero-ref "field V34._upper (fldOffset=0x8)" P-INDEP ;* V83 tmp75 [V83 ] ( 0, 0 ) long -> zero-ref "field V35._lower (fldOffset=0x0)" P-INDEP ;* V84 tmp76 [V84 ] ( 0, 0 ) long -> zero-ref "field V35._upper (fldOffset=0x8)" P-INDEP ;* V85 tmp77 [V85 ] ( 0, 0 ) long -> zero-ref "field V37._lower (fldOffset=0x0)" P-INDEP ;* V86 tmp78 [V86 ] ( 0, 0 ) long -> zero-ref "field V37._upper (fldOffset=0x8)" P-INDEP ;* V87 tmp79 [V87 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V41.Item1 (fldOffset=0x0)" P-DEP ;* V88 tmp80 [V88 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V41.Item2 (fldOffset=0x8)" P-DEP -; V89 tmp81 [V89,T12] ( 4, 16 ) long -> rax "field V42.Item1 (fldOffset=0x0)" P-INDEP +; V89 tmp81 [V89,T12] ( 4, 16 ) long -> rsi "field V42.Item1 (fldOffset=0x0)" P-INDEP ; V90 tmp82 [V90,T13] ( 4, 16 ) long -> rdx "field V42.Item2 (fldOffset=0x8)" P-INDEP ;* V91 tmp83 [V91 ] ( 0, 0 ) long -> zero-ref "field V45._lower (fldOffset=0x0)" P-INDEP ;* V92 tmp84 [V92 ] ( 0, 0 ) long -> zero-ref "field V45._upper (fldOffset=0x8)" P-INDEP ; V93 rat0 [V93,T22] ( 4, 0.13) long -> [rbp-0x80] "Strength reduced derived IV" ; V94 rat1 [V94,T23] ( 4, 0.13) int -> [rbp-0x84] "Trip count IV" ; V95 rat2 [V95,T20] ( 4, 1.00) int -> [rbp-0x88] "Trip count IV" ; V96 rat3 [V96,T14] ( 4, 12.38) long -> [rbp-0x90] "Strength reduced derived IV" ; V97 rat4 [V97,T15] ( 4, 12.38) int -> [rbp-0x94] "Trip count IV" ; V98 rat5 [V98,T00] ( 4, 99 ) int -> [rbp-0x98] "Trip count IV" ; ; Lcl frame size = 120 G_M56689_IG01: push rbp push r15 push r14 push r13 push r12 push rbx sub rsp, 120 lea rbp, [rsp+0xA0] mov rbx, rdi mov r13, rsi mov r12d, edx mov r15, rcx mov r14, r8 ;; size=37 bbWeight=1 PerfScore 8.00 G_M56689_IG02: - mov rax, r15 - shr rax, 32 - sete r9b - movzx r9, r9b - mov dword ptr [rbp-0x2C], r9d - lea eax, [r12-0x01] - test eax, eax + mov rdx, r15 + shr rdx, 32 + sete al + movzx rax, al + mov dword ptr [rbp-0x2C], eax + lea edx, [r12-0x01] + test edx, edx jle G_M56689_IG12 - ;; size=32 bbWeight=1 PerfScore 4.25 + ;; size=29 bbWeight=1 PerfScore 4.25 G_M56689_IG03: - lea eax, [r12-0x01] - cmp eax, r12d + lea edx, [r12-0x01] + cmp edx, r12d jg G_M56689_IG22 - xor r10d, r10d - lea r11d, [r12-0x01] - mov dword ptr [rbp-0x94], r11d + xor r9d, r9d + lea r10d, [r12-0x01] + mov dword ptr [rbp-0x94], r10d ;; size=29 bbWeight=0.50 PerfScore 1.75 G_M56689_IG04: - mov qword ptr [rbp-0x90], r10 - mov rdi, qword ptr [r10+r13] + mov qword ptr [rbp-0x90], r9 + mov r11, qword ptr [r9+r13] mov dword ptr [rbp-0x98], 64 ;; size=21 bbWeight=3.96 PerfScore 15.84 G_M56689_IG05: - test r9d, r9d + test eax, eax jne SHORT G_M56689_IG08 - ;; size=5 bbWeight=31.68 PerfScore 39.60 + ;; size=4 bbWeight=31.68 PerfScore 39.60 G_M56689_IG06: - mov qword ptr [rbp-0x38], rdi - test dil, 1 + mov qword ptr [rbp-0x38], r11 + test r11b, 1 je SHORT G_M56689_IG07 - mov rax, rbx - mul rdx:rax, r14 - mov rsi, rax + mov rdx, rbx + mulx rdx, rsi, r14 mov rcx, r15 xor r8d, r8d lea rdi, [rbp-0x58] - mov rax, 0xD1FFAB1E ; code for System.UInt128:DivRem(System.UInt128,System.UInt128):System.ValueTuple`2[System.UInt128,System.UInt128] - call [rax]System.UInt128:DivRem(System.UInt128,System.UInt128):System.ValueTuple`2[System.UInt128,System.UInt128] + mov r14, 0xD1FFAB1E ; code for System.UInt128:DivRem(System.UInt128,System.UInt128):System.ValueTuple`2[System.UInt128,System.UInt128] + call [r14]System.UInt128:DivRem(System.UInt128,System.UInt128):System.ValueTuple`2[System.UInt128,System.UInt128] mov r14, qword ptr [rbp-0x48] - ;; size=45 bbWeight=7.92 PerfScore 87.12 + ;; size=45 bbWeight=7.92 PerfScore 85.14 G_M56689_IG07: - mov rax, rbx - mul rdx:rax, rbx - mov rsi, rax + mov rdx, rbx + mulx rdx, rsi, rbx mov rcx, r15 xor r8d, r8d lea rdi, [rbp-0x78] - mov rax, 0xD1FFAB1E ; code for System.UInt128:DivRem(System.UInt128,System.UInt128):System.ValueTuple`2[System.UInt128,System.UInt128] - call [rax]System.UInt128:DivRem(System.UInt128,System.UInt128):System.ValueTuple`2[System.UInt128,System.UInt128] + mov rbx, 0xD1FFAB1E ; code for System.UInt128:DivRem(System.UInt128,System.UInt128):System.ValueTuple`2[System.UInt128,System.UInt128] + call [rbx]System.UInt128:DivRem(System.UInt128,System.UInt128):System.ValueTuple`2[System.UInt128,System.UInt128] mov rbx, qword ptr [rbp-0x68] - mov rdi, qword ptr [rbp-0x38] + mov r11, qword ptr [rbp-0x38] jmp SHORT G_M56689_IG10 - ;; size=41 bbWeight=7.92 PerfScore 93.06 + ;; size=40 bbWeight=7.92 PerfScore 91.08 G_M56689_IG08: - test dil, 1 + test r11b, 1 je SHORT G_M56689_IG09 mov rax, r14 imul rax, rbx xor edx, edx div rdx:rax, r15 mov r14d, edx ;; size=21 bbWeight=7.92 PerfScore 514.80 G_M56689_IG09: mov rax, rbx imul rax, rbx xor edx, edx div rdx:rax, r15 mov ebx, edx ;; size=14 bbWeight=7.92 PerfScore 504.90 G_M56689_IG10: - shr rdi, 1 - mov r8d, dword ptr [rbp-0x98] - dec r8d - mov dword ptr [rbp-0x98], r8d - mov r9d, dword ptr [rbp-0x2C] + shr r11, 1 + mov edi, dword ptr [rbp-0x98] + dec edi + mov dword ptr [rbp-0x98], edi + mov eax, dword ptr [rbp-0x2C] jne G_M56689_IG05 - ;; size=30 bbWeight=31.68 PerfScore 150.48 + ;; size=26 bbWeight=31.68 PerfScore 150.48 G_M56689_IG11: - mov r10, qword ptr [rbp-0x90] - add r10, 8 - mov r11d, dword ptr [rbp-0x94] - dec r11d - mov dword ptr [rbp-0x94], r11d + mov r9, qword ptr [rbp-0x90] + add r9, 8 + mov r10d, dword ptr [rbp-0x94] + dec r10d + mov dword ptr [rbp-0x94], r10d jne G_M56689_IG04 ;; size=34 bbWeight=3.96 PerfScore 17.82 G_M56689_IG12: lea esi, [r12-0x01] cmp esi, r12d jae G_M56689_IG23 mov rsi, qword ptr [r13+8*rsi] mov rdi, rbx mov rdx, r15 mov rcx, r14 mov rax, 0xD1FFAB1E ; code for System.Numerics.BigIntegerCalculator:PowCore(nuint,nuint,nuint,nuint):nuint ;; size=38 bbWeight=1 PerfScore 4.75 G_M56689_IG13: add rsp, 120 pop rbx pop r12 pop r13 pop r14 pop r15 pop rbp tail.jmp [rax]System.Numerics.BigIntegerCalculator:PowCore(nuint,nuint,nuint,nuint):nuint ;; size=17 bbWeight=1 PerfScore 5.25 G_M56689_IG14: - test dil, 1 + test r11b, 1 je SHORT G_M56689_IG15 mov rax, r14 imul rax, rbx xor edx, edx div rdx:rax, r15 mov r14d, edx ;; size=21 bbWeight=0.08 PerfScore 5.20 G_M56689_IG15: mov rax, rbx imul rax, rbx xor edx, edx div rdx:rax, r15 mov ebx, edx - mov qword ptr [rbp-0x38], rdi + mov qword ptr [rbp-0x38], r11 ;; size=18 bbWeight=0.08 PerfScore 5.18 G_M56689_IG16: - mov rdi, qword ptr [rbp-0x38] - shr rdi, 1 - mov r8d, dword ptr [rbp-0x88] - dec r8d - mov dword ptr [rbp-0x88], r8d - mov r9d, dword ptr [rbp-0x2C] + mov r11, qword ptr [rbp-0x38] + shr r11, 1 + mov edi, dword ptr [rbp-0x88] + dec edi + mov dword ptr [rbp-0x88], edi + mov eax, dword ptr [rbp-0x2C] jne SHORT G_M56689_IG19 - ;; size=30 bbWeight=0.32 PerfScore 1.84 + ;; size=26 bbWeight=0.32 PerfScore 1.84 G_M56689_IG17: - mov r10, qword ptr [rbp-0x80] - add r10, 8 - mov r11d, dword ptr [rbp-0x84] - dec r11d - mov dword ptr [rbp-0x84], r11d + mov r9, qword ptr [rbp-0x80] + add r9, 8 + mov r10d, dword ptr [rbp-0x84] + dec r10d + mov dword ptr [rbp-0x84], r10d je G_M56689_IG12 ;; size=31 bbWeight=0.04 PerfScore 0.18 G_M56689_IG18: - mov qword ptr [rbp-0x80], r10 - mov rdi, qword ptr [r10+r13] + mov qword ptr [rbp-0x80], r9 + mov r11, qword ptr [r9+r13] mov dword ptr [rbp-0x88], 64 ;; size=18 bbWeight=0.04 PerfScore 0.16 G_M56689_IG19: - test r9d, r9d + test eax, eax jne SHORT G_M56689_IG14 - ;; size=5 bbWeight=0.32 PerfScore 0.40 + ;; size=4 bbWeight=0.32 PerfScore 0.40 G_M56689_IG20: - mov qword ptr [rbp-0x38], rdi - test dil, 1 + mov qword ptr [rbp-0x38], r11 + test r11b, 1 je SHORT G_M56689_IG21 - mov rax, rbx - mul rdx:rax, r14 - mov rsi, rax + mov rdx, rbx + mulx rdx, rsi, r14 mov rcx, r15 xor r8d, r8d lea rdi, [rbp-0x58] - mov rax, 0xD1FFAB1E ; code for System.UInt128:DivRem(System.UInt128,System.UInt128):System.ValueTuple`2[System.UInt128,System.UInt128] - call [rax]System.UInt128:DivRem(System.UInt128,System.UInt128):System.ValueTuple`2[System.UInt128,System.UInt128] + mov r14, 0xD1FFAB1E ; code for System.UInt128:DivRem(System.UInt128,System.UInt128):System.ValueTuple`2[System.UInt128,System.UInt128] + call [r14]System.UInt128:DivRem(System.UInt128,System.UInt128):System.ValueTuple`2[System.UInt128,System.UInt128] mov r14, qword ptr [rbp-0x48] - ;; size=45 bbWeight=0.08 PerfScore 0.88 + ;; size=45 bbWeight=0.08 PerfScore 0.86 G_M56689_IG21: - mov rax, rbx - mul rdx:rax, rbx - mov rsi, rax + mov rdx, rbx + mulx rdx, rsi, rbx mov rcx, r15 xor r8d, r8d lea rdi, [rbp-0x78] - mov rax, 0xD1FFAB1E ; code for System.UInt128:DivRem(System.UInt128,System.UInt128):System.ValueTuple`2[System.UInt128,System.UInt128] - call [rax]System.UInt128:DivRem(System.UInt128,System.UInt128):System.ValueTuple`2[System.UInt128,System.UInt128] + mov rbx, 0xD1FFAB1E ; code for System.UInt128:DivRem(System.UInt128,System.UInt128):System.ValueTuple`2[System.UInt128,System.UInt128] + call [rbx]System.UInt128:DivRem(System.UInt128,System.UInt128):System.ValueTuple`2[System.UInt128,System.UInt128] mov rbx, qword ptr [rbp-0x68] jmp G_M56689_IG16 - ;; size=40 bbWeight=0.08 PerfScore 0.86 + ;; size=39 bbWeight=0.08 PerfScore 0.84 G_M56689_IG22: - xor r10d, r10d - lea r11d, [r12-0x01] - mov dword ptr [rbp-0x84], r11d + xor r9d, r9d + lea r10d, [r12-0x01] + mov dword ptr [rbp-0x84], r10d jmp SHORT G_M56689_IG18 ;; size=17 bbWeight=0.01 PerfScore 0.02 G_M56689_IG23: call CORINFO_HELP_RNGCHKFAIL int3 ;; size=6 bbWeight=0 PerfScore 0.00 -; Total bytes of code 595, prolog size 37, PerfScore 1462.34, instruction count 154, allocated bytes for code 595 (MethodHash=166d228e) for method System.Numerics.BigIntegerCalculator:PowCore(nuint,System.ReadOnlySpan`1[nuint],nuint,nuint):nuint (FullOpts) +; Total bytes of code 580, prolog size 37, PerfScore 1458.34, instruction count 150, allocated bytes for code 580 (MethodHash=166d228e) for method System.Numerics.BigIntegerCalculator:PowCore(nuint,System.ReadOnlySpan`1[nuint],nuint,nuint):nuint (FullOpts) ; ============================================================ ```
-15 (-6.52 % of base) - System.Random+XoshiroImpl:NextInt64(long,long):long:this ```diff ; Assembly listing for method System.Random+XoshiroImpl:NextInt64(long,long):long:this (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rbp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 2 single block inlinees; 3 inlinees without PGO data ; Final local variable assignments ; ; V00 this [V00,T00] ( 18, 42 ) ref -> rdi this class-hnd single-def ; V01 arg1 [V01,T14] ( 4, 4 ) long -> rsi single-def ; V02 arg2 [V02,T17] ( 3, 3 ) long -> rdx single-def ;# V03 OutArgs [V03 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ; V04 tmp1 [V04,T05] ( 6, 16 ) long -> rcx "Inlining Arg" ; V05 tmp2 [V05,T07] ( 5, 10.50) long -> r8 ld-addr-op "Inline ldloca(s) first use temp" ; V06 tmp3 [V06,T15] ( 3, 6 ) long -> r9 "Inline stloc first use temp" ; V07 tmp4 [V07,T18] ( 3, 5 ) long -> [rbp-0x10] spill-single-def "Inline stloc first use temp" -; V08 tmp5 [V08,T16] ( 5, 5 ) long -> rax "Inline stloc first use temp" -; V09 tmp6 [V09,T11] ( 7, 7 ) long -> rdx "Inline stloc first use temp" +; V08 tmp5 [V08,T16] ( 5, 5 ) long -> rdx "Inline stloc first use temp" +; V09 tmp6 [V09,T11] ( 7, 7 ) long -> rax "Inline stloc first use temp" ; V10 tmp7 [V10,T12] ( 7, 7 ) long -> r8 "Inline stloc first use temp" ; V11 tmp8 [V11,T13] ( 7, 7 ) long -> r9 "Inline stloc first use temp" ; V12 tmp9 [V12,T20] ( 2, 2 ) long -> r10 "Inline stloc first use temp" ; V13 tmp10 [V13,T19] ( 2, 4 ) long -> r11 "impSpillLclRefs" ;* V14 tmp11 [V14 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V15 tmp12 [V15 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V16 tmp13 [V16 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" -; V17 tmp14 [V17,T04] ( 5, 20 ) long -> rax "Inline stloc first use temp" -; V18 tmp15 [V18,T01] ( 7, 28 ) long -> r8 "Inline stloc first use temp" -; V19 tmp16 [V19,T02] ( 7, 28 ) long -> r9 "Inline stloc first use temp" +; V17 tmp14 [V17,T04] ( 5, 20 ) long -> r8 "Inline stloc first use temp" +; V18 tmp15 [V18,T01] ( 7, 28 ) long -> r9 "Inline stloc first use temp" +; V19 tmp16 [V19,T02] ( 7, 28 ) long -> rax "Inline stloc first use temp" ; V20 tmp17 [V20,T03] ( 7, 28 ) long -> r10 "Inline stloc first use temp" ; V21 tmp18 [V21,T08] ( 2, 8 ) long -> r11 "Inline stloc first use temp" ; V22 tmp19 [V22,T06] ( 2, 16 ) long -> rbx "impSpillLclRefs" ;* V23 tmp20 [V23 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V24 tmp21 [V24 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V25 tmp22 [V25 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V26 tmp23 [V26 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V15.Item1 (fldOffset=0x0)" P-DEP ;* V27 tmp24 [V27 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V15.Item2 (fldOffset=0x8)" P-DEP ; V28 tmp25 [V28,T21] ( 2, 2 ) long -> r8 "field V16.Item1 (fldOffset=0x0)" P-INDEP ; V29 tmp26 [V29,T22] ( 2, 2 ) long -> r9 "field V16.Item2 (fldOffset=0x8)" P-INDEP ;* V30 tmp27 [V30 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V24.Item1 (fldOffset=0x0)" P-DEP ;* V31 tmp28 [V31 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V24.Item2 (fldOffset=0x8)" P-DEP ; V32 tmp29 [V32,T09] ( 2, 8 ) long -> r8 "field V25.Item1 (fldOffset=0x0)" P-INDEP ; V33 tmp30 [V33,T10] ( 2, 8 ) long -> r9 "field V25.Item2 (fldOffset=0x8)" P-INDEP ; ; Lcl frame size = 8 G_M20492_IG01: push rbp push rbx push rax lea rbp, [rsp+0x10] ;; size=8 bbWeight=1 PerfScore 3.50 G_M20492_IG02: mov rcx, rdx sub rcx, rsi - mov rax, qword ptr [rdi+0x08] - mov rdx, qword ptr [rdi+0x10] + mov rdx, qword ptr [rdi+0x08] + mov rax, qword ptr [rdi+0x10] mov r8, qword ptr [rdi+0x18] mov r9, qword ptr [rdi+0x20] - mov r10, rdx + mov r10, rax shl r10, 17 - xor r8, rax - xor r9, rdx - lea r11, [rdx+4*rdx] + xor r8, rdx + xor r9, rax + lea r11, [rax+4*rax] rol r11, 7 lea r11, [r11+8*r11] - xor rdx, r8 - xor rax, r9 + xor rax, r8 + xor rdx, r9 xor r8, r10 rol r9, 45 - mov qword ptr [rdi+0x08], rax - mov qword ptr [rdi+0x10], rdx + mov qword ptr [rdi+0x08], rdx + mov qword ptr [rdi+0x10], rax mov qword ptr [rdi+0x18], r8 mov qword ptr [rdi+0x20], r9 - mov rax, rcx - mul rdx:rax, r11 - mov r8, rax - mov r9, rdx + mov rdx, rcx + mulx r9, r8, r11 cmp r8, rcx jae SHORT G_M20492_IG05 - ;; NOP compensation instructions of 4 bytes. - ;; size=97 bbWeight=1 PerfScore 21.50 + ;; size=89 bbWeight=1 PerfScore 21.00 G_M20492_IG03: mov rax, rcx neg rax xor edx, edx div rdx:rax, rcx mov qword ptr [rbp-0x10], rdx cmp r8, rdx jae SHORT G_M20492_IG05 - align [3 bytes for IG04] - ;; size=23 bbWeight=0.50 PerfScore 32.12 + align [0 bytes for IG04] + ;; size=20 bbWeight=0.50 PerfScore 32.00 G_M20492_IG04: - mov rax, qword ptr [rdi+0x08] - mov r8, qword ptr [rdi+0x10] - mov r9, qword ptr [rdi+0x18] + mov r8, qword ptr [rdi+0x08] + mov r9, qword ptr [rdi+0x10] + mov rax, qword ptr [rdi+0x18] mov r10, qword ptr [rdi+0x20] - mov r11, r8 + mov r11, r9 shl r11, 17 - xor r9, rax - xor r10, r8 - lea rbx, [r8+4*r8] + xor rax, r8 + xor r10, r9 + lea rbx, [r9+4*r9] rol rbx, 7 lea rbx, [rbx+8*rbx] - xor r8, r9 - xor rax, r10 - xor r9, r11 + xor r9, rax + xor r8, r10 + xor rax, r11 rol r10, 45 - mov qword ptr [rdi+0x08], rax - mov qword ptr [rdi+0x10], r8 - mov qword ptr [rdi+0x18], r9 + mov qword ptr [rdi+0x08], r8 + mov qword ptr [rdi+0x10], r9 + mov qword ptr [rdi+0x18], rax mov qword ptr [rdi+0x20], r10 - mov rax, rcx - mul rdx:rax, rbx - mov r8, rax - mov r9, rdx + mov rdx, rcx + mulx r9, r8, rbx mov rdx, qword ptr [rbp-0x10] cmp r8, rdx jb SHORT G_M20492_IG04 - ;; size=91 bbWeight=4 PerfScore 88.00 + ;; size=87 bbWeight=4 PerfScore 86.00 G_M20492_IG05: lea rax, [r9+rsi] ;; size=4 bbWeight=1 PerfScore 0.50 G_M20492_IG06: add rsp, 8 pop rbx pop rbp ret ;; size=7 bbWeight=1 PerfScore 2.25 -; Total bytes of code 230, prolog size 8, PerfScore 147.88, instruction count 70, allocated bytes for code 230 (MethodHash=f394aff3) for method System.Random+XoshiroImpl:NextInt64(long,long):long:this (FullOpts) +; Total bytes of code 215, prolog size 8, PerfScore 145.25, instruction count 66, allocated bytes for code 215 (MethodHash=f394aff3) for method System.Random+XoshiroImpl:NextInt64(long,long):long:this (FullOpts) ; ============================================================ ```
-14 (-41.18 % of base) - System.Int128:op_Multiply(System.Int128,System.Int128):System.Int128 ```diff ; Assembly listing for method System.Int128:op_Multiply(System.Int128,System.Int128):System.Int128 (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rsp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 8 single block inlinees; 1 inlinees without PGO data ; Final local variable assignments ; ;* V00 arg0 [V00 ] ( 0, 0 ) struct (16) zero-ref multireg-arg single-def ;* V01 arg1 [V01 ] ( 0, 0 ) struct (16) zero-ref multireg-arg single-def ;# V02 OutArgs [V02 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ;* V03 tmp1 [V03 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V04 tmp2 [V04 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V05 tmp3 [V05 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V06 tmp4 [V06 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V07 tmp5 [V07 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V08 tmp6 [V08 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V09 tmp7 [V09 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V10 tmp8 [V10 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V11 tmp9 [V11 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V12 tmp10 [V12 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V13 tmp11 [V13 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V14 tmp12 [V14 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V15 tmp13 [V15 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V16 tmp14 [V16 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V17 tmp15 [V17 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V18 tmp16 [V18 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V19 tmp17 [V19 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V20 tmp18 [V20 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V21 tmp19 [V21,T02] ( 2, 4 ) long -> rdx "Inlining Arg" ;* V22 tmp20 [V22 ] ( 0, 0 ) struct (16) zero-ref multireg-ret ld-addr-op "NewObj constructor temp" ;* V23 tmp21 [V23 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V24 tmp22 [V24 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V25 tmp23 [V25,T00] ( 3, 3 ) long -> rdi single-def "field V00._lower (fldOffset=0x0)" P-INDEP ; V26 tmp24 [V26,T03] ( 2, 2 ) long -> rsi single-def "field V00._upper (fldOffset=0x8)" P-INDEP -; V27 tmp25 [V27,T01] ( 3, 3 ) long -> [rsp+0x00] single-def "field V01._lower (fldOffset=0x0)" P-INDEP +; V27 tmp25 [V27,T01] ( 3, 3 ) long -> rdx single-def "field V01._lower (fldOffset=0x0)" P-INDEP ; V28 tmp26 [V28,T04] ( 2, 2 ) long -> rcx single-def "field V01._upper (fldOffset=0x8)" P-INDEP ;* V29 tmp27 [V29 ] ( 0, 0 ) long -> zero-ref "field V03._lower (fldOffset=0x0)" P-INDEP ;* V30 tmp28 [V30 ] ( 0, 0 ) long -> zero-ref "field V03._upper (fldOffset=0x8)" P-INDEP ;* V31 tmp29 [V31 ] ( 0, 0 ) long -> zero-ref "field V04._lower (fldOffset=0x0)" P-INDEP ;* V32 tmp30 [V32 ] ( 0, 0 ) long -> zero-ref "field V04._upper (fldOffset=0x8)" P-INDEP ;* V33 tmp31 [V33 ] ( 0, 0 ) long -> zero-ref "field V05._lower (fldOffset=0x0)" P-INDEP ;* V34 tmp32 [V34 ] ( 0, 0 ) long -> zero-ref "field V05._upper (fldOffset=0x8)" P-INDEP ;* V35 tmp33 [V35 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V06._lower (fldOffset=0x0)" P-DEP ;* V36 tmp34 [V36 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V06._upper (fldOffset=0x8)" P-DEP ;* V37 tmp35 [V37 ] ( 0, 0 ) long -> zero-ref "field V07._lower (fldOffset=0x0)" P-INDEP ;* V38 tmp36 [V38 ] ( 0, 0 ) long -> zero-ref "field V07._upper (fldOffset=0x8)" P-INDEP ;* V39 tmp37 [V39 ] ( 0, 0 ) long -> zero-ref "field V10._lower (fldOffset=0x0)" P-INDEP ;* V40 tmp38 [V40 ] ( 0, 0 ) long -> zero-ref "field V10._upper (fldOffset=0x8)" P-INDEP ;* V41 tmp39 [V41 ] ( 0, 0 ) long -> zero-ref "field V14._lower (fldOffset=0x0)" P-INDEP ;* V42 tmp40 [V42 ] ( 0, 0 ) long -> zero-ref "field V14._upper (fldOffset=0x8)" P-INDEP ;* V43 tmp41 [V43 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V18.Item1 (fldOffset=0x0)" P-DEP ;* V44 tmp42 [V44 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V18.Item2 (fldOffset=0x8)" P-DEP ; V45 tmp43 [V45,T05] ( 2, 2 ) long -> rax "field V19.Item1 (fldOffset=0x0)" P-INDEP -; V46 tmp44 [V46,T06] ( 2, 2 ) long -> rdx "field V19.Item2 (fldOffset=0x8)" P-INDEP +; V46 tmp44 [V46,T06] ( 2, 2 ) long -> r8 "field V19.Item2 (fldOffset=0x8)" P-INDEP ;* V47 tmp45 [V47 ] ( 0, 0 ) long -> zero-ref "field V22._lower (fldOffset=0x0)" P-INDEP ;* V48 tmp46 [V48 ] ( 0, 0 ) long -> zero-ref "field V22._upper (fldOffset=0x8)" P-INDEP ; -; Lcl frame size = 8 +; Lcl frame size = 0 G_M34075_IG01: - push rax - ;; size=1 bbWeight=1 PerfScore 1.00 + ;; size=0 bbWeight=1 PerfScore 0.00 G_M34075_IG02: - mov qword ptr [rsp], rdx - mov rax, rdi - mul rdx:rax, rdx + mulx r8, rax, rdi imul rcx, rdi - mov rdi, qword ptr [rsp] - imul rdi, rsi - add rdx, rdi + imul rdx, rsi + add rdx, r8 add rdx, rcx - ;; size=28 bbWeight=1 PerfScore 9.75 + ;; size=19 bbWeight=1 PerfScore 7.50 G_M34075_IG03: - add rsp, 8 ret - ;; size=5 bbWeight=1 PerfScore 1.25 + ;; size=1 bbWeight=1 PerfScore 1.00 -; Total bytes of code 34, prolog size 1, PerfScore 12.00, instruction count 11, allocated bytes for code 34 (MethodHash=76857ae4) for method System.Int128:op_Multiply(System.Int128,System.Int128):System.Int128 (FullOpts) +; Total bytes of code 20, prolog size 0, PerfScore 8.50, instruction count 6, allocated bytes for code 20 (MethodHash=76857ae4) for method System.Int128:op_Multiply(System.Int128,System.Int128):System.Int128 (FullOpts) ; ============================================================ ```
-14 (-25.45 % of base) - System.Int128:System.Numerics.INumberBase.MultiplyAddEstimate(System.Int128,System.Int128,System.Int128):System.Int128 ```diff ; Assembly listing for method System.Int128:System.Numerics.INumberBase.MultiplyAddEstimate(System.Int128,System.Int128,System.Int128):System.Int128 (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rsp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 11 single block inlinees; 1 inlinees without PGO data ; Final local variable assignments ; ;* V00 arg0 [V00 ] ( 0, 0 ) struct (16) zero-ref multireg-arg single-def ;* V01 arg1 [V01 ] ( 0, 0 ) struct (16) zero-ref multireg-arg single-def ;* V02 arg2 [V02 ] ( 0, 0 ) struct (16) zero-ref multireg-arg single-def ;# V03 OutArgs [V03 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ;* V04 tmp1 [V04 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V05 tmp2 [V05 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V06 tmp3 [V06 ] ( 0, 0 ) struct (16) zero-ref "impAppendStmt" ;* V07 tmp4 [V07 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V08 tmp5 [V08 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V09 tmp6 [V09 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V10 tmp7 [V10 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V11 tmp8 [V11 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V12 tmp9 [V12 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V13 tmp10 [V13 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V14 tmp11 [V14 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V15 tmp12 [V15 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V16 tmp13 [V16 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V17 tmp14 [V17 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V18 tmp15 [V18 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V19 tmp16 [V19 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V20 tmp17 [V20 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V21 tmp18 [V21 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V22 tmp19 [V22 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V23 tmp20 [V23,T02] ( 2, 4 ) long -> rdx "Inlining Arg" ;* V24 tmp21 [V24 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V25 tmp22 [V25 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V26 tmp23 [V26 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V27 tmp24 [V27,T07] ( 3, 3 ) long -> r8 "Inline stloc first use temp" ; V28 tmp25 [V28,T09] ( 2, 2 ) long -> rax "Inline stloc first use temp" ;* V29 tmp26 [V29 ] ( 0, 0 ) struct (16) zero-ref multireg-ret ld-addr-op "NewObj constructor temp" ;* V30 tmp27 [V30 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V31 tmp28 [V31,T00] ( 3, 3 ) long -> rdi single-def "field V00._lower (fldOffset=0x0)" P-INDEP ; V32 tmp29 [V32,T03] ( 2, 2 ) long -> rsi single-def "field V00._upper (fldOffset=0x8)" P-INDEP -; V33 tmp30 [V33,T01] ( 3, 3 ) long -> [rsp+0x00] single-def "field V01._lower (fldOffset=0x0)" P-INDEP +; V33 tmp30 [V33,T01] ( 3, 3 ) long -> rdx single-def "field V01._lower (fldOffset=0x0)" P-INDEP ; V34 tmp31 [V34,T04] ( 2, 2 ) long -> rcx single-def "field V01._upper (fldOffset=0x8)" P-INDEP ; V35 tmp32 [V35,T05] ( 2, 2 ) long -> r8 single-def "field V02._lower (fldOffset=0x0)" P-INDEP ; V36 tmp33 [V36,T06] ( 2, 2 ) long -> r9 single-def "field V02._upper (fldOffset=0x8)" P-INDEP ;* V37 tmp34 [V37 ] ( 0, 0 ) long -> zero-ref "field V04._lower (fldOffset=0x0)" P-INDEP ;* V38 tmp35 [V38 ] ( 0, 0 ) long -> zero-ref "field V04._upper (fldOffset=0x8)" P-INDEP ;* V39 tmp36 [V39 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V05._lower (fldOffset=0x0)" P-DEP ;* V40 tmp37 [V40 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V05._upper (fldOffset=0x8)" P-DEP ;* V41 tmp38 [V41 ] ( 0, 0 ) long -> zero-ref "field V06._lower (fldOffset=0x0)" P-INDEP ;* V42 tmp39 [V42 ] ( 0, 0 ) long -> zero-ref "field V06._upper (fldOffset=0x8)" P-INDEP ;* V43 tmp40 [V43 ] ( 0, 0 ) long -> zero-ref "field V07._lower (fldOffset=0x0)" P-INDEP ;* V44 tmp41 [V44 ] ( 0, 0 ) long -> zero-ref "field V07._upper (fldOffset=0x8)" P-INDEP ;* V45 tmp42 [V45 ] ( 0, 0 ) long -> zero-ref "field V08._lower (fldOffset=0x0)" P-INDEP ;* V46 tmp43 [V46 ] ( 0, 0 ) long -> zero-ref "field V08._upper (fldOffset=0x8)" P-INDEP ;* V47 tmp44 [V47 ] ( 0, 0 ) long -> zero-ref "field V09._lower (fldOffset=0x0)" P-INDEP ;* V48 tmp45 [V48 ] ( 0, 0 ) long -> zero-ref "field V09._upper (fldOffset=0x8)" P-INDEP ;* V49 tmp46 [V49 ] ( 0, 0 ) long -> zero-ref "field V12._lower (fldOffset=0x0)" P-INDEP ;* V50 tmp47 [V50 ] ( 0, 0 ) long -> zero-ref "field V12._upper (fldOffset=0x8)" P-INDEP ;* V51 tmp48 [V51 ] ( 0, 0 ) long -> zero-ref "field V16._lower (fldOffset=0x0)" P-INDEP ;* V52 tmp49 [V52 ] ( 0, 0 ) long -> zero-ref "field V16._upper (fldOffset=0x8)" P-INDEP ;* V53 tmp50 [V53 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V20.Item1 (fldOffset=0x0)" P-DEP ;* V54 tmp51 [V54 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V20.Item2 (fldOffset=0x8)" P-DEP ; V55 tmp52 [V55,T08] ( 3, 3 ) long -> rax "field V21.Item1 (fldOffset=0x0)" P-INDEP -; V56 tmp53 [V56,T10] ( 2, 2 ) long -> rdx "field V21.Item2 (fldOffset=0x8)" P-INDEP +; V56 tmp53 [V56,T10] ( 2, 2 ) long -> r10 "field V21.Item2 (fldOffset=0x8)" P-INDEP ;* V57 tmp54 [V57 ] ( 0, 0 ) long -> zero-ref "field V24._lower (fldOffset=0x0)" P-INDEP ;* V58 tmp55 [V58 ] ( 0, 0 ) long -> zero-ref "field V24._upper (fldOffset=0x8)" P-INDEP ;* V59 tmp56 [V59 ] ( 0, 0 ) long -> zero-ref "field V29._lower (fldOffset=0x0)" P-INDEP ; V60 tmp57 [V60,T11] ( 2, 2 ) long -> rdx "field V29._upper (fldOffset=0x8)" P-INDEP ; -; Lcl frame size = 8 +; Lcl frame size = 0 G_M63118_IG01: - push rax - ;; size=1 bbWeight=1 PerfScore 1.00 + ;; size=0 bbWeight=1 PerfScore 0.00 G_M63118_IG02: - mov qword ptr [rsp], rdx - mov rax, rdi - mul rdx:rax, rdx + mulx r10, rax, rdi imul rcx, rdi - mov rdi, qword ptr [rsp] - imul rdi, rsi - add rdx, rdi + imul rdx, rsi + add rdx, r10 add rdx, rcx add r8, rax cmp r8, rax setb al movzx rax, al add rdx, r9 add rdx, rax mov rax, r8 - ;; size=49 bbWeight=1 PerfScore 11.75 + ;; size=40 bbWeight=1 PerfScore 9.50 G_M63118_IG03: - add rsp, 8 ret - ;; size=5 bbWeight=1 PerfScore 1.25 + ;; size=1 bbWeight=1 PerfScore 1.00 -; Total bytes of code 55, prolog size 1, PerfScore 14.00, instruction count 18, allocated bytes for code 55 (MethodHash=1cf40971) for method System.Int128:System.Numerics.INumberBase.MultiplyAddEstimate(System.Int128,System.Int128,System.Int128):System.Int128 (FullOpts) +; Total bytes of code 41, prolog size 0, PerfScore 10.50, instruction count 13, allocated bytes for code 41 (MethodHash=1cf40971) for method System.Int128:System.Numerics.INumberBase.MultiplyAddEstimate(System.Int128,System.Int128,System.Int128):System.Int128 (FullOpts) ; ============================================================ ```
-14 (-41.18 % of base) - System.UInt128:op_Multiply(System.UInt128,System.UInt128):System.UInt128 ```diff ; Assembly listing for method System.UInt128:op_Multiply(System.UInt128,System.UInt128):System.UInt128 (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rsp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 1 inlinees without PGO data ; Final local variable assignments ; ;* V00 arg0 [V00 ] ( 0, 0 ) struct (16) zero-ref multireg-arg single-def ;* V01 arg1 [V01 ] ( 0, 0 ) struct (16) zero-ref multireg-arg single-def ;* V02 loc0 [V02 ] ( 0, 0 ) long -> zero-ref ld-addr-op ;# V03 OutArgs [V03 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ;* V04 tmp1 [V04 ] ( 0, 0 ) struct (16) zero-ref multireg-ret ld-addr-op "NewObj constructor temp" ;* V05 tmp2 [V05 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V06 tmp3 [V06 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V07 tmp4 [V07 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V08 tmp5 [V08 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V09 tmp6 [V09 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V10 tmp7 [V10 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V11 tmp8 [V11,T02] ( 2, 4 ) long -> rdx "Inlining Arg" ; V12 tmp9 [V12,T00] ( 3, 3 ) long -> rdi single-def "field V00._lower (fldOffset=0x0)" P-INDEP ; V13 tmp10 [V13,T03] ( 2, 2 ) long -> rsi single-def "field V00._upper (fldOffset=0x8)" P-INDEP -; V14 tmp11 [V14,T01] ( 3, 3 ) long -> [rsp+0x00] single-def "field V01._lower (fldOffset=0x0)" P-INDEP +; V14 tmp11 [V14,T01] ( 3, 3 ) long -> rdx single-def "field V01._lower (fldOffset=0x0)" P-INDEP ; V15 tmp12 [V15,T04] ( 2, 2 ) long -> rcx single-def "field V01._upper (fldOffset=0x8)" P-INDEP ;* V16 tmp13 [V16 ] ( 0, 0 ) long -> zero-ref "field V04._lower (fldOffset=0x0)" P-INDEP ;* V17 tmp14 [V17 ] ( 0, 0 ) long -> zero-ref "field V04._upper (fldOffset=0x8)" P-INDEP ;* V18 tmp15 [V18 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V08.Item1 (fldOffset=0x0)" P-DEP ;* V19 tmp16 [V19 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V08.Item2 (fldOffset=0x8)" P-DEP ; V20 tmp17 [V20,T05] ( 2, 2 ) long -> rax "field V09.Item1 (fldOffset=0x0)" P-INDEP -; V21 tmp18 [V21,T06] ( 2, 2 ) long -> rdx "field V09.Item2 (fldOffset=0x8)" P-INDEP +; V21 tmp18 [V21,T06] ( 2, 2 ) long -> r8 "field V09.Item2 (fldOffset=0x8)" P-INDEP ; -; Lcl frame size = 8 +; Lcl frame size = 0 G_M8731_IG01: - push rax - ;; size=1 bbWeight=1 PerfScore 1.00 + ;; size=0 bbWeight=1 PerfScore 0.00 G_M8731_IG02: - mov qword ptr [rsp], rdx - mov rax, rdi - mul rdx:rax, rdx + mulx r8, rax, rdi imul rcx, rdi - mov rdi, qword ptr [rsp] - imul rdi, rsi - add rdx, rdi + imul rdx, rsi + add rdx, r8 add rdx, rcx - ;; size=28 bbWeight=1 PerfScore 9.75 + ;; size=19 bbWeight=1 PerfScore 7.50 G_M8731_IG03: - add rsp, 8 ret - ;; size=5 bbWeight=1 PerfScore 1.25 + ;; size=1 bbWeight=1 PerfScore 1.00 -; Total bytes of code 34, prolog size 1, PerfScore 12.00, instruction count 11, allocated bytes for code 34 (MethodHash=4ac8dde4) for method System.UInt128:op_Multiply(System.UInt128,System.UInt128):System.UInt128 (FullOpts) +; Total bytes of code 20, prolog size 0, PerfScore 8.50, instruction count 6, allocated bytes for code 20 (MethodHash=4ac8dde4) for method System.UInt128:op_Multiply(System.UInt128,System.UInt128):System.UInt128 (FullOpts) ; ============================================================ ```
-14 (-25.45 % of base) - System.UInt128:System.Numerics.INumberBase.MultiplyAddEstimate(System.UInt128,System.UInt128,System.UInt128):System.UInt128 ```diff ; Assembly listing for method System.UInt128:System.Numerics.INumberBase.MultiplyAddEstimate(System.UInt128,System.UInt128,System.UInt128):System.UInt128 (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rsp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 4 single block inlinees; 1 inlinees without PGO data ; Final local variable assignments ; ;* V00 arg0 [V00 ] ( 0, 0 ) struct (16) zero-ref multireg-arg single-def ;* V01 arg1 [V01 ] ( 0, 0 ) struct (16) zero-ref multireg-arg single-def ;* V02 arg2 [V02 ] ( 0, 0 ) struct (16) zero-ref multireg-arg single-def ;# V03 OutArgs [V03 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ;* V04 tmp1 [V04 ] ( 0, 0 ) struct (16) zero-ref "spilled call-like call argument" ;* V05 tmp2 [V05 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V06 tmp3 [V06 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V07 tmp4 [V07 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V08 tmp5 [V08 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V09 tmp6 [V09 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V10 tmp7 [V10 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V11 tmp8 [V11 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V12 tmp9 [V12 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V13 tmp10 [V13 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V14 tmp11 [V14,T02] ( 2, 4 ) long -> rdx "Inlining Arg" ; V15 tmp12 [V15,T07] ( 3, 3 ) long -> r8 "Inline stloc first use temp" ; V16 tmp13 [V16,T09] ( 2, 2 ) long -> rax "Inline stloc first use temp" ;* V17 tmp14 [V17 ] ( 0, 0 ) struct (16) zero-ref multireg-ret ld-addr-op "NewObj constructor temp" ;* V18 tmp15 [V18 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ; V19 tmp16 [V19,T00] ( 3, 3 ) long -> rdi single-def "field V00._lower (fldOffset=0x0)" P-INDEP ; V20 tmp17 [V20,T03] ( 2, 2 ) long -> rsi single-def "field V00._upper (fldOffset=0x8)" P-INDEP -; V21 tmp18 [V21,T01] ( 3, 3 ) long -> [rsp+0x00] single-def "field V01._lower (fldOffset=0x0)" P-INDEP +; V21 tmp18 [V21,T01] ( 3, 3 ) long -> rdx single-def "field V01._lower (fldOffset=0x0)" P-INDEP ; V22 tmp19 [V22,T04] ( 2, 2 ) long -> rcx single-def "field V01._upper (fldOffset=0x8)" P-INDEP ; V23 tmp20 [V23,T05] ( 2, 2 ) long -> r8 single-def "field V02._lower (fldOffset=0x0)" P-INDEP ; V24 tmp21 [V24,T06] ( 2, 2 ) long -> r9 single-def "field V02._upper (fldOffset=0x8)" P-INDEP ;* V25 tmp22 [V25 ] ( 0, 0 ) long -> zero-ref "field V04._lower (fldOffset=0x0)" P-INDEP ;* V26 tmp23 [V26 ] ( 0, 0 ) long -> zero-ref "field V04._upper (fldOffset=0x8)" P-INDEP ;* V27 tmp24 [V27 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V05._lower (fldOffset=0x0)" P-DEP ;* V28 tmp25 [V28 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V05._upper (fldOffset=0x8)" P-DEP ;* V29 tmp26 [V29 ] ( 0, 0 ) long -> zero-ref "field V07._lower (fldOffset=0x0)" P-INDEP ;* V30 tmp27 [V30 ] ( 0, 0 ) long -> zero-ref "field V07._upper (fldOffset=0x8)" P-INDEP ;* V31 tmp28 [V31 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V11.Item1 (fldOffset=0x0)" P-DEP ;* V32 tmp29 [V32 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V11.Item2 (fldOffset=0x8)" P-DEP ; V33 tmp30 [V33,T08] ( 3, 3 ) long -> rax "field V12.Item1 (fldOffset=0x0)" P-INDEP -; V34 tmp31 [V34,T10] ( 2, 2 ) long -> rdx "field V12.Item2 (fldOffset=0x8)" P-INDEP +; V34 tmp31 [V34,T10] ( 2, 2 ) long -> r10 "field V12.Item2 (fldOffset=0x8)" P-INDEP ;* V35 tmp32 [V35 ] ( 0, 0 ) long -> zero-ref "field V17._lower (fldOffset=0x0)" P-INDEP ; V36 tmp33 [V36,T11] ( 2, 2 ) long -> rdx "field V17._upper (fldOffset=0x8)" P-INDEP ; -; Lcl frame size = 8 +; Lcl frame size = 0 G_M33934_IG01: - push rax - ;; size=1 bbWeight=1 PerfScore 1.00 + ;; size=0 bbWeight=1 PerfScore 0.00 G_M33934_IG02: - mov qword ptr [rsp], rdx - mov rax, rdi - mul rdx:rax, rdx + mulx r10, rax, rdi imul rcx, rdi - mov rdi, qword ptr [rsp] - imul rdi, rsi - add rdx, rdi + imul rdx, rsi + add rdx, r10 add rdx, rcx add r8, rax cmp r8, rax setb al movzx rax, al add rdx, r9 add rdx, rax mov rax, r8 - ;; size=49 bbWeight=1 PerfScore 11.75 + ;; size=40 bbWeight=1 PerfScore 9.50 G_M33934_IG03: - add rsp, 8 ret - ;; size=5 bbWeight=1 PerfScore 1.25 + ;; size=1 bbWeight=1 PerfScore 1.00 -; Total bytes of code 55, prolog size 1, PerfScore 14.00, instruction count 18, allocated bytes for code 55 (MethodHash=76e07b71) for method System.UInt128:System.Numerics.INumberBase.MultiplyAddEstimate(System.UInt128,System.UInt128,System.UInt128):System.UInt128 (FullOpts) +; Total bytes of code 41, prolog size 0, PerfScore 10.50, instruction count 13, allocated bytes for code 41 (MethodHash=76e07b71) for method System.UInt128:System.Numerics.INumberBase.MultiplyAddEstimate(System.UInt128,System.UInt128,System.UInt128):System.UInt128 (FullOpts) ; ============================================================ ```
-13 (-7.34 % of base) - System.IO.Hashing.XxHashShared:MergeAccumulators(ptr,ptr,ulong):ulong ```diff ; Assembly listing for method System.IO.Hashing.XxHashShared:MergeAccumulators(ptr,ptr,ulong):ulong (FullOpts) ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix ; FullOpts code ; optimized code ; rbp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 11 single block inlinees; 12 inlinees without PGO data ; Final local variable assignments ; ; V00 arg0 [V00,T00] ( 10, 10 ) long -> rdi single-def ; V01 arg1 [V01,T01] ( 10, 10 ) long -> rsi single-def ; V02 arg2 [V02,T03] ( 3, 3 ) long -> [rbp-0x08] single-def ;# V03 OutArgs [V03 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ;* V04 tmp1 [V04 ] ( 0, 0 ) long -> zero-ref "impAppendStmt" ;* V05 tmp2 [V05 ] ( 0, 0 ) long -> zero-ref "impAppendStmt" ;* V06 tmp3 [V06 ] ( 0, 0 ) long -> zero-ref "impAppendStmt" -; V07 tmp4 [V07,T04] ( 2, 4 ) long -> [rbp-0x10] spill-single-def "impAppendStmt" +; V07 tmp4 [V07,T04] ( 2, 4 ) long -> rax "impAppendStmt" ;* V08 tmp5 [V08 ] ( 0, 0 ) long -> zero-ref "impAppendStmt" ;* V09 tmp6 [V09 ] ( 0, 0 ) long -> zero-ref "impAppendStmt" ;* V10 tmp7 [V10 ] ( 0, 0 ) long -> zero-ref "impAppendStmt" -; V11 tmp8 [V11,T05] ( 2, 4 ) long -> [rbp-0x18] spill-single-def "impAppendStmt" +; V11 tmp8 [V11,T05] ( 2, 4 ) long -> rax "impAppendStmt" ;* V12 tmp9 [V12 ] ( 0, 0 ) long -> zero-ref "impAppendStmt" ;* V13 tmp10 [V13 ] ( 0, 0 ) long -> zero-ref "impAppendStmt" ;* V14 tmp11 [V14 ] ( 0, 0 ) long -> zero-ref "impAppendStmt" -; V15 tmp12 [V15,T06] ( 2, 4 ) long -> [rbp-0x20] spill-single-def "impAppendStmt" +; V15 tmp12 [V15,T06] ( 2, 4 ) long -> rax "impAppendStmt" ;* V16 tmp13 [V16 ] ( 0, 0 ) long -> zero-ref "impAppendStmt" ;* V17 tmp14 [V17 ] ( 0, 0 ) long -> zero-ref "impAppendStmt" ;* V18 tmp15 [V18 ] ( 0, 0 ) long -> zero-ref "impAppendStmt" ;* V19 tmp16 [V19 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V20 tmp17 [V20 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V21 tmp18 [V21 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V22 tmp19 [V22 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V23 tmp20 [V23 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V24 tmp21 [V24 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V25 tmp22 [V25 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V26 tmp23 [V26 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[SBRM] multireg-ret multireg-dest "Return value temp for multireg return" ;* V27 tmp24 [V27 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Inline stloc first use temp" ;* V28 tmp25 [V28 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V29 tmp26 [V29 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V30 tmp27 [V30 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V31 tmp28 [V31 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V32 tmp29 [V32 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V33 tmp30 [V33 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V34 tmp31 [V34 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V35 tmp32 [V35 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V36 tmp33 [V36 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Return value temp for multireg return" ;* V37 tmp34 [V37 ] ( 0, 0 ) struct (16) zero-ref "Inline stloc first use temp" ;* V38 tmp35 [V38 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V39 tmp36 [V39 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V40 tmp37 [V40 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V41 tmp38 [V41 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V42 tmp39 [V42 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V43 tmp40 [V43 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V44 tmp41 [V44 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V45 tmp42 [V45 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V46 tmp43 [V46 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Return value temp for multireg return" ;* V47 tmp44 [V47 ] ( 0, 0 ) struct (16) zero-ref "Inline stloc first use temp" ;* V48 tmp45 [V48 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V49 tmp46 [V49 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V50 tmp47 [V50 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V51 tmp48 [V51 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V52 tmp49 [V52 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V53 tmp50 [V53 ] ( 0, 0 ) long -> zero-ref ld-addr-op "Inline ldloca(s) first use temp" ;* V54 tmp51 [V54 ] ( 0, 0 ) long -> zero-ref "Inline stloc first use temp" ;* V55 tmp52 [V55 ] ( 0, 0 ) long -> zero-ref "Inline return value spill temp" ;* V56 tmp53 [V56 ] ( 0, 0 ) struct (16) zero-ref multireg-ret multireg-dest "Return value temp for multireg return" ;* V57 tmp54 [V57 ] ( 0, 0 ) struct (16) zero-ref "Inline stloc first use temp" ; V58 tmp55 [V58,T02] ( 6, 12 ) long -> rax "Inlining Arg" ;* V59 tmp56 [V59 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V26.Item1 (fldOffset=0x0)" P-DEP ;* V60 tmp57 [V60 ] ( 0, 0 ) long -> zero-ref do-not-enreg[] "field V26.Item2 (fldOffset=0x8)" P-DEP ; V61 tmp58 [V61,T07] ( 2, 2 ) long -> rax "field V27.Item1 (fldOffset=0x0)" P-INDEP -; V62 tmp59 [V62,T08] ( 2, 2 ) long -> rdx "field V27.Item2 (fldOffset=0x8)" P-INDEP -; V63 tmp60 [V63,T09] ( 2, 2 ) long -> rax "field V36.Item1 (fldOffset=0x0)" P-INDEP -; V64 tmp61 [V64,T10] ( 2, 2 ) long -> rdx "field V36.Item2 (fldOffset=0x8)" P-INDEP +; V62 tmp59 [V62,T08] ( 2, 2 ) long -> rcx "field V27.Item2 (fldOffset=0x8)" P-INDEP +; V63 tmp60 [V63,T09] ( 2, 2 ) long -> rcx "field V36.Item1 (fldOffset=0x0)" P-INDEP +; V64 tmp61 [V64,T10] ( 2, 2 ) long -> r8 "field V36.Item2 (fldOffset=0x8)" P-INDEP ;* V65 tmp62 [V65 ] ( 0, 0 ) long -> zero-ref "field V37.Item1 (fldOffset=0x0)" P-INDEP ;* V66 tmp63 [V66 ] ( 0, 0 ) long -> zero-ref "field V37.Item2 (fldOffset=0x8)" P-INDEP -; V67 tmp64 [V67,T11] ( 2, 2 ) long -> rax "field V46.Item1 (fldOffset=0x0)" P-INDEP -; V68 tmp65 [V68,T12] ( 2, 2 ) long -> rdx "field V46.Item2 (fldOffset=0x8)" P-INDEP +; V67 tmp64 [V67,T11] ( 2, 2 ) long -> rcx "field V46.Item1 (fldOffset=0x0)" P-INDEP +; V68 tmp65 [V68,T12] ( 2, 2 ) long -> r8 "field V46.Item2 (fldOffset=0x8)" P-INDEP ;* V69 tmp66 [V69 ] ( 0, 0 ) long -> zero-ref "field V47.Item1 (fldOffset=0x0)" P-INDEP ;* V70 tmp67 [V70 ] ( 0, 0 ) long -> zero-ref "field V47.Item2 (fldOffset=0x8)" P-INDEP -; V71 tmp68 [V71,T13] ( 2, 2 ) long -> rax "field V56.Item1 (fldOffset=0x0)" P-INDEP +; V71 tmp68 [V71,T13] ( 2, 2 ) long -> rcx "field V56.Item1 (fldOffset=0x0)" P-INDEP ; V72 tmp69 [V72,T14] ( 2, 2 ) long -> rdx "field V56.Item2 (fldOffset=0x8)" P-INDEP ;* V73 tmp70 [V73 ] ( 0, 0 ) long -> zero-ref "field V57.Item1 (fldOffset=0x0)" P-INDEP ;* V74 tmp71 [V74 ] ( 0, 0 ) long -> zero-ref "field V57.Item2 (fldOffset=0x8)" P-INDEP ; -; Lcl frame size = 32 +; Lcl frame size = 16 G_M38428_IG01: push rbp - sub rsp, 32 - lea rbp, [rsp+0x20] + sub rsp, 16 + lea rbp, [rsp+0x10] mov qword ptr [rbp-0x08], rdx ;; size=14 bbWeight=1 PerfScore 2.75 G_M38428_IG02: mov rax, qword ptr [rdi] xor rax, qword ptr [rsi] mov rcx, qword ptr [rdi+0x08] xor rcx, qword ptr [rsi+0x08] - mul rdx:rax, rcx - xor rax, rdx + mov rdx, rax + mulx rcx, rax, rcx + xor rax, rcx add rax, qword ptr [rbp-0x08] - mov qword ptr [rbp-0x10], rax mov rdx, qword ptr [rdi+0x10] xor rdx, qword ptr [rsi+0x10] mov rcx, qword ptr [rdi+0x18] xor rcx, qword ptr [rsi+0x18] - mov rax, rcx - mul rdx:rax, rdx - xor rax, rdx - add rax, qword ptr [rbp-0x10] - mov qword ptr [rbp-0x18], rax + mulx r8, rcx, rcx + xor rcx, r8 + add rax, rcx mov rdx, qword ptr [rdi+0x20] xor rdx, qword ptr [rsi+0x20] mov rcx, qword ptr [rdi+0x28] xor rcx, qword ptr [rsi+0x28] - mov rax, rcx - mul rdx:rax, rdx - xor rax, rdx - add rax, qword ptr [rbp-0x18] - mov qword ptr [rbp-0x20], rax + mulx r8, rcx, rcx + xor rcx, r8 + add rax, rcx mov rdx, qword ptr [rdi+0x30] xor rdx, qword ptr [rsi+0x30] mov rcx, qword ptr [rdi+0x38] xor rcx, qword ptr [rsi+0x38] - mov rax, rcx - mul rdx:rax, rdx - xor rax, rdx - add rax, qword ptr [rbp-0x20] + mulx rdx, rcx, rcx + xor rcx, rdx + add rax, rcx mov rcx, rax shr rcx, 37 xor rcx, rax mov rax, 0xD1FFAB1E imul rax, rcx mov rcx, rax shr rcx, 32 xor rax, rcx - ;; size=157 bbWeight=1 PerfScore 57.00 + ;; size=144 bbWeight=1 PerfScore 51.25 G_M38428_IG03: - add rsp, 32 + add rsp, 16 pop rbp ret ;; size=6 bbWeight=1 PerfScore 1.75 -; Total bytes of code 177, prolog size 10, PerfScore 61.50, instruction count 49, allocated bytes for code 177 (MethodHash=34fb69e3) for method System.IO.Hashing.XxHashShared:MergeAccumulators(ptr,ptr,ulong):ulong (FullOpts) +; Total bytes of code 164, prolog size 10, PerfScore 55.75, instruction count 44, allocated bytes for code 164 (MethodHash=34fb69e3) for method System.IO.Hashing.XxHashShared:MergeAccumulators(ptr,ptr,ulong):ulong (FullOpts) ; ============================================================ ```